|
|
|
| 82540EP Architecture |
|
|
| |||||
|
|
|
|
|
| Flash Interface |
|
|
|
|
| |
|
|
|
|
|
|
|
|
|
|
|
| MDI |
|
|
|
|
|
|
|
|
|
|
|
| (Copper) |
|
|
| Target | Control, Status |
|
|
|
| PHY | Interface | ||
|
|
| & Interrupt | Flash | MDIO |
|
|
| ||||
|
|
| Control |
|
|
| ||||||
|
|
| Registers |
|
|
|
|
|
|
| ||
|
|
|
|
|
|
|
|
|
|
| ||
|
|
|
| Target Logic |
|
|
|
| GMII |
| ||
| PCI |
|
|
|
|
|
|
|
|
| MAC Core |
|
|
|
| DMA |
|
|
| Tx |
|
|
| ||
| Core |
|
|
| TX |
|
|
|
| |||
PCI |
|
|
|
|
|
|
| TX MAC |
| |||
|
|
|
|
|
| Arb |
|
| ||||
PCI I/F |
|
| TX |
|
| Out |
|
|
| |||
i/f | read |
| AlignmentData |
| BufferPacketInterface | RegisterCSR Access | DataTX |
| RX Data |
| ||
| engine |
|
|
|
| |||||||
|
|
|
| descriptor | TX |
|
|
|
|
| TX |
|
| Master |
|
| engine |
|
|
|
|
|
| Link |
|
| write |
|
| FIFOs |
|
| Flow |
|
|
| RX MAC |
|
| FIFO |
|
|
|
|
| Ctrl |
|
|
|
|
|
|
|
| RX |
|
|
|
|
|
|
|
| |
|
|
|
|
|
|
|
|
|
|
|
| |
| Master |
| descriptor | RX |
|
|
|
|
|
|
| |
| FIFO |
|
| FIFOs |
|
| RX |
| RX Data |
|
| |
|
|
|
|
|
|
| In |
|
|
| Filter |
|
|
|
|
|
|
|
|
|
|
|
|
| |
| (Many | ACPI | LED |
|
|
|
|
|
|
|
|
|
| blocks) |
|
|
|
|
|
| CSR Register |
| |||
|
|
|
|
|
|
|
|
|
| |||
|
| Clock / Reset |
| 64K bytes |
|
| Access |
| ||||
|
|
| HW |
|
|
|
|
|
| |||
|
| EEPROM |
|
|
|
|
|
|
|
|
| |
Silicon |
| Default |
|
|
|
|
| Manageability |
|
| ||
|
|
|
|
|
|
|
|
|
| |||
|
|
| Configs | Packet Buffer |
| Mgmt | ASF | Statistics |
| |||
|
|
|
| FIFOs |
| |||||||
|
|
|
|
|
|
|
|
|
|
| ||
|
|
|
|
|
| SMBus Interface |
|
| ||||
|
|
|
|
|
|
|
|
| ||||
Datasheet
Figure 1. Gigabit Ethernet Controller Block Diagram
2
