Networking Silicon — 82540EP
Datasheet 1
1.0 Introduction
The Intel® 82540EP Gigabit Ethernet Controller is a single, compact compone nt wi th an inte g rated
Gigabit Ethernet Media Access Control (MAC) and physical layer (PHY) functions. For desktop,
workstation and mobile PC Network designs with critica l s p ac e constraints, the Intel® 82540EP
allows for a Gigabi t Ethernet impleme ntation in a very small area that is footprint compat ible with
current generation 10/100 Mbps Fast Ethernet designs
The Intel® 82540EP integrates Intel’s fourth generation gigabit MAC design with fully integrated,
physical layer circuitry to provide a standard IEEE 802.3 Ethernet interface for 1000BASE-T,
100BASE-TX, and 10BASE-T applications (80 2.3, 802.3u, and 802. 3ab) . The cont roller i s cap able
of transmitting and receiving data at rates of 1000 Mbps, 100 Mbps, or 10 Mbps. In addition to
managing MAC and PHY layer functions, the controller provides a 32-bit wide direct Peripheral
Component Interconnect (PCI) 2.2 compliant interface capab le of ope rating at 33 or 66 MHz.
The 82540EP also incorporates the CLKRUN protocol and hardware suppo rted downshift
capability to two or three-pair 100 Mb/s operation. These features optimize mobile applications.
The Intel® 82540EP’s on-board System Management Bus (SMB) port enables network
manageability implementations required by in formation technology personnel for remote control
and alerting via the LAN. With SMB, management packets can be routed to or from a management
processor. The S MB p o rt enables industry standards, such as Intelligent Platform Management
Interface (IPMI) and Alert Standard Forum (ASF), to be implemented using the 82540EP. In
addition, on chip ASF 1.0 circuitry provides alert ing and remote control capabilities with
standardized interfaces.
The 82540EP Gigabit Ethernet Controller architecture is designed to deliver high performance and
PCI bus efficiency. Wide internal data path s eli m i n at e p er f o rm an c e bo t tl e necks by efficiently
handling large address and data words. The 82540EP controller includes advanced interrupt
handling features to limit PCI bus traffi c and a PCI interface that maximizes the use of bursts for
efficient bus usage. The 82540EP caches up to 64 pack et descriptors in a single burst for efficient
PCI bandwidth use. A large 64 KByte on-chip packet buffer mai ntains superior performance as
available PCI bandwidth changes. In addition, using hardware acceleration, the controller offloads
tasks from the host controller, such as TCP/UDP/IP che cksum calculations and TCP segmentation.
The 82540EP is packaged in a 15 mm2 196-ball grid array and is pin compatible with both the
82551QM 10/100 Mbps Fast Ethernet Multifunction PCI/CardBus Controller and the 82540EM
Gigabit Ethernet Controller (which does not have add ed power saving features like CLKRUN).