82540EP — Networking Silicon
8Datasheet
2.6 Additional Device Features
2.7 Technology Features
Features Benefits
Four activity and link indication outputs that directly
drive LEDs • Link and activity indicatio ns (10, 100, and 10 00
Mbps) on each port
Programmable LED functio nality • Softwar e definable function (speed, link, and
activity) and blinki ng allowing flexible LED
implementations
Internal PLL for clock generation c an use a 25 MHz
crystal • Low er component count and system cost
JTAG (IEE E 1149.1) Test Access Port built in silicon • Simplified testing using boundary scan
On-chip power control circuitrya
a. If applying the “low-power” EEPRO M setting for the 82540EP chip, th en only external voltage regulator c ircuits should be used
instead of the on-chip power control circuitr y
• Reduced number of on-board power supply
regulators
• Simplified power supply desi gn in less power-
critical applicatio ns
Four software definabl e pins • Additional flexibility for LEDs or other low speed
I/O devices
Supports little endian byte ordering for both 32 and 64
bit systems and big endi an byt e ord ering for 64 bit
systems • Portable across application archi tectures
Two or three-pair cable downshift • Supports modular hardware access ories
Provides loopback capa bi li ties • Validates silicon integrity
Minimal ballout ch ange from the 8254 0EM • Pin Compatibility
Features Benefits
196-pin Ball Grid Array (TFBGA) package • 15 mm2 component making LOM designs easier
Pin compatible with 82551QM and 82540EM
controllers
• Enables 10/100 Mbps Fast Etherne t or 1000 Mbps
Gigabit Etherne t implementations on the same
board with only minor stuffing option changes
Implemented in 0.15u CM OS process • Offers lowest geometry to minimize power and
size while mainta ining Intel quality re liability
standards
Operating temperat ure: 0° C to 70° C (maximum)
operating temperature
Heat sink or forced ai rflow not required
65° C to 140° C storage temperature range
• Simple thermal design
PCI Signaling: 3.3 V (5 V tolerant) PCI signaling
Typical targeted power dissipatio n:
• 1.38W @ D0 1000 Mb/s
• 386mW @ D 3 100 Mb/s (wake-up enabled)
• <20mW @ D3 wake-up disabled
• Lower power requirements for mobi le applications