Intel MD566X manual Parallel Host Interface 16C450/16C550A Uart, Programmer’s Guide, 119

56K V.92 Data, Fax, and Voice Chipset

10.PARALLEL HOST INTERFACE 16C450/16C550A

UART

The parallel host interface of the MD566X family emulate the electrical and register functions of a 16550A and 16C450 UART. Upon modem reset, the modem defaults to a 16C450. The host (DTE) can then configure the UART to function as a 16C550A UART.

In 16C450 emulation mode, the DTE and modem transfer data back and forth a byte at a time. In 16C550A emulation mode, the modem provides two 16-byte FIFO buffers, one for the transmitter and another for the receiver. Thus, up to 16 bytes of data may be sent to or received from the modem for each data interrupt, instead of only a single byte, as in 16C450 mode. The following diagram shows how the FIFO is used. Host software using this FIFO capability can significantly reduce system overhead by reducing the number of times that interrupt service routines are called.

Modem

Transmitter

Shift

Register

Modem

Receiver

Shift

Register

	UART
	Transmitter
Modem Transmitter FIFO	Holding
	Register
	(THR)
UART Transmitter Flow Diagram
	UART
	Receiver
Modem Receiver FIFO	Buffer
	Register
	(RBR)

UART Receiver Flow Diagram

Host (DTE)

Host (DTE)

Figure 10-1. FIFO Buffers for Transmitter and Receiver

The register addresses are divided into two types: single-register access and multiple-register access. Most of the UART registers are single-register access (that is, only one internal register is accessible for a given register address). UART register addresses 3–7 are used to access a single internal register. The remainder of the UART register addresses (0–2) are used to access two or more internal registers.

Register address 2 is used to write FIFO control information into the FCR (FIFO Control register) and to read the IIR (Interrupt Identity register).

Register address 1 is used to read and write data to the IER (Interrupt Enable register) [when DLAB = 0] and the MS DLM (Divisor Latch register) [when DLAB = 1].

Register address 0 is used to read data from the RBR (Receiver Buffer register) [when DLAB = 0], write data to the THR (Transmitter Holding register) [when DLAB = 0], and read and write to the LS DLL (Divisor Latch register) [when DLAB = 1]. The UART registers and FIFO usage are described in the following sections.

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