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Intel MD566X 10. PARALLEL HOST INTERFACE 16C450/16C550A UART

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Programmer’s Guide Intel Confide ntial 119

10. PARALLEL HOST INTERFACE 16C450/16C550A UART

The parallel host interface of the MD566X family emulate the electrical and register functions of a

16550A and 16C450 UART. Upon modem reset, the modem defaults to a 16C450. The host (DTE)

can then configure the UART to function as a 16C550A UART.

In 16C450 emulation mode, the DTE and modem transfer data back and forth a byte at a time. In

16C550A emulation mode, the modem provides two 16-byte FIFO buffers, one for the transmitter

and another for the receiver. Thus, up to 16 bytes of data may be sent to or received from the

modem for each data interrupt, instead of only a single byte, as in 16C450 mode. The following

diagram shows how the FIFO is used. Host software using this FIFO capability can significantly

reduce system overhead by reducing the number of times that interrupt service routines are called.

Figure 10-1. FIFO Buffers for Transmitter and Receiver

The register addresses are divided into two types: single-register access and multiple-register

access. Most of the UART registers are single-register access (that is, only one internal register is

accessible for a given register address). UART register addresses 3–7 are used to access a single

internal register. The remainder of the UART register addresses (0–2) are used to access two or

more internal registers.

Register address 2 is used to write FIFO control information into the FCR (FIFO Control register)

and to read the IIR (Interrupt Identity register).

Register address 1 is used to read and write data to the IER (Interrupt Enable register) [when

DLAB = 0] and the MS DLM (Divisor Latch register) [when DLAB = 1].

Register address 0 is used to read data from the RBR (Receiver Buffer register) [when DLAB = 0],

write data to the THR (Transmitter Holding register) [when DLAB = 0], and read and write to the

LS DLL (Divisor Latch register) [when DLAB = 1]. The UART registers and FIFO usage are

described in the following sections.

Modem Transmitter FIFO

Transmitter Transmitter

(THR)

Register

Holding

Shift

Register

UART Transmitter Flow Diagram

Modem Receiver FIFO

Receiver Receiver

(RBR)

Register

Buffer

Shift

Register

UART Receiver Flow Diagram

UART

UART

Modem

Modem

Host

(DTE)

Host

(DTE)

Contents

Main MD566X 56K Data, Fax, and Voice Chipset Revision History Date Revision May 2001 Revise layout. July 2001 Update for V.92 Programmers Guide Intel Confidential CONVENTIONS Abbreviations Acronyms Acronym Definition (Continued) Programmers Guide Intel Confidential 1. INTRODUCTION Table 1-1. Intel V.90/V.92 56K Chipsets 1.1 V.92, V.90 and V.34 Data Modes 1.2 Modem Connection Overview Programmers Guide Intel Confidential Table 1-2. DTE-to-DCE Data Rates for Each Mode Table 1-3. DCE-to-DCE Data Rates for Each Mode 2. AT COMMAND SUMMARY TABLES Table 2-1. Data Mode Command Summary Note Command Function Default Range Reported by &Vn 56K V.92 Data, Fax, and Voice Chipset Note Command Function Default Range Reported by &Vn Page Page Page Page 14 Intel Confidential Programmers Guide Table 2-2. V.44 / V.42 / V.42 bis MNP Command Summary Note Command Function Default Range Reported by &Vn Programmers Guide Intel Confidential Table 2-2. V.44 / V.42 / V.42 bis MNP Command Summary (Continued) Note Command Function Default Range Reported by &Vn Page Programmers Guide Intel Confidential Table 2-3. Fax Identity Command Summary Table 2-4. Fax Class 1 Command Summary Table 2-5. IS-101 Voice Command Summary 18 Intel Confidential Programmers Guide Table 2-5. IS-101 Voice Command Summary (Continued) Table 2-6. Voice DTEDCE Character Pairs Response Hex Code Function Programmers Guide Intel Confidential Table 2-7. Voice DTEDCE Character Pairs Response Hex Code Function 20 Intel Confidential Programmers Guide Table 2-8. Dial Modifiers Command Function Note R egister Function Default Range Units Table 2-9. S-Register Summary Reported by &Vn Programmers Guide Intel Confidential Table 2-9. S-Register Summary (Continued) Table 2-10. V.90/V.92 Mode DCE-to-ISP Response Codes 22 Intel Confidential Programmers Guide Table 2-11. V.34 Mode DCE-to-DCE Response Codes Verbose Code Numeric Code Table 2-12. DTE-to-DCE Data Rate Response Codes Verbose Code Numeric Code Programmers Guide Intel Confidential Table 2-13. Manufacturing-Only Command Summary 3. BASIC DATA MODE AT COMMANDS 3.1 Using AT Commands to Access the S-Registers [Sn?, Sn=x, ?] 3.2 Modem Responses and Command Echo [En, Vn, Xn, Wn, Qn] Programmers Guide Intel Confidential 3.3 Modem Reset and NVRAM Commands [DS=n, Zn, &F, &Vn, &Yn, &Wn, &Zn=x] Table 3-1. Product Identification Information 3.5 Establishing a Modem Connection [A, D, DS = n, S0] 3.6 Online Command Mode [Escape Codes, On] 3.7 Hanging Up [Hn, S10, Zn, &D2] 3.8 Modem-to-Modem Connection Data Rates Page Page Page Page Programmers Guide Intel Confidential Table 3-2. Supported Modulation Types Page Programmers Guide Intel Confidential Table 3-3. Resulting DCE-to-DCE Connection Rates with Non-Default Value s 3.9 Diagnostic Testing [S18, &Tn] 3.9.1 Local Analog Loopback [AT&T1] LOCAL MODEM Figure 3-2. Local Analog Loopback Test Local Modem (or Test Modem) Page 3.9.2 Local Analog Loopback With Self-Test [AT&T8] Figure 3-3. Local Analog Loopback with Self-Test Local Modem (or Test Modem) Programmers Guide Intel Confidential 3.10 AT Escape Sequences 3.10.1 Time-Independent Escape Sequence Licensing Requirements for Hayes Escape Sequence 3.10.2 Hayes Escape Sequence En, Hn, Mn, On, Qn, Sn, Vn, Xn, and & commands (except &Tn and &F) Page Page Page Page Programmers Guide Intel Confidential (cont.) 0 Identification/Checksum Option: (cont.) Page Page Programmers Guide Intel Confidential Wn 0 Page Page Page Page Page Page Page Page Page Page Page Page Page Programmers Guide Intel Confidential 4. ERROR CORRECTION AND DATA COMPRESSION Operating Modes Table 4-1. Resulting \Nn Connection Types Page Page Page Page Page Page +DS44=m 3,0,0,471, 972,140, 140,1884, 3768 5. FAX CLASS 1 AT COMMANDS 5.1 Fax Identity Commands Table 5-1. Fax Identity Command Descriptions Programmers Guide Intel Confidential Table 5-1. Fax Identity Command Descriptions 5.2 Fax Clas s 1 Commands Figure 5-1. T.30 HDLC Frame Format Table 5-2. <mod> Selection Table Programmers Guide Intel Confidential Figure 5-2. CLASS 1 DTE-Generated HDLC Frame Information (AT+FTH=<mod>) Figure 5-3. CLASS 1 DTE Reception of HDLC Frame Information (AT+FRH=<mod>) Table 5-3. Fax Mode Command Descriptions Page Page 6. IS-101 VOICE MODE AT COMMANDS 6.1 DTMF Detection 6.2 Relay Control Table 6-1. Voice Mode Command Descriptions Page Page Page Page Programmers Guide Intel Confidential Table 6-1. Voice Mode Command Descriptions (Continued) 15678 2 } } Page Programmers Guide Intel Confidential +VLS=n 0 Preassigned Voice I/O Labels Table 6-1. Voice Mode Command Descriptions (Continued) <label> Primitive Code Description Voice I/O Primitive Codes Table 6-1. Voice Mode Command Descriptions (Continued) Page Page Page Page Page Page Page Page Page Page Programmers Guide Intel Confidential 7. S-REGISTERS Table 7-1. S-Register Command Descriptions Page Page Page Page Page Programmers Guide Intel Confidential S33 10 Page Page Programmers Guide Intel Confidential 8. CALLER ID Table 8-1. Caller ID Tags for Formatted Reporting Page Programmers Guide Intel Confidential 9. MANUFACTURING-ONLY COMMANDS Table 9-1. Manufacturing-Only Command Descriptions Page Page Page Page Page 10. PARALLEL HOST INTERFACE 16C450/16C550A UART Figure 10-1. FIFO Buffers for Transmitter and Receiver 120 Intel Confidential Programmers Guide Table 10-1. Parallel Host Interface UART Register Bit Assignments Note: These bits are always 0 in 16C450 mode. 10.1 UART Register Definitions 10.1.1 Scratch Register (SCR) Register 5 10.1.2 Modem Status Register (MSR) 10.1.3 Line Status Register (LSR) 10.1.4 Modem Control Register (MCR) Register 4 10.1.5 Line Control Register (LCR) Register 3 10.1.6 FIFO Control Register (FCR) Register 2 Programmers Guide Intel Confide ntial 125 10.1.7 Interrupt Identity Register (IIR) Table 10-2. Interrupt Control Functions FIFO Mode Only Interrupt Identification Register Interrupt Source and Reset Functions FIFO EN FIFO EN 0 VDMA Int. ID 2 Int. ID 1 Int. ID 0 Int. Pen. 10.1.8 Interrupt Enable Register (IER) 10.1.9 Transmitter Holding Register (THR) 10.1.10Receiver Buffer Register (RBR) Register 1 10.1.11Divisor Latch Registers (DLM and DLL) 10.2 16C550A UART FIFO Operation 10.2.1 FIFO Interrupt Mode Operation Table 10-3. Programmable Data Rates Register 1 10.2.2 FIFO Polled Mode Operation