Intel MD566X manual Interrupt Identity Register IIR, Interrupt Control Functions, 125

56K V.92 Data, Fax, and Voice Chipset

10.1.7 Interrupt Identity Register (IIR)

Register 2

(read-only)

FIFO EN FIFO EN

0

VDMA

Int. ID 2

Int. ID 1

Int. ID 0

Int. Pen.

This read-only register indicates when the transmitter and receiver FIFOs are enabled, and the source of highest-priority pending interrupt to the DTE. Five levels of modem interrupt sources in order of priority are: receiver line status, received data ready, character time-out indication, transmitter holding register empty, and modem status. When the DTE reads the IIR, the modem freezes all interrupts and indicates the highest-priority pending interrupt. While the DTE is reading the IIR register, the modem records new interrupts but does not change its current indication until the read process is completed.

Table 10-2. Interrupt Control Functions

FIFO		Interrupt
Mode	Identification					Interrupt Source and Reset Functions
Only			Register
Bit 3	Bit 2		Bit 1	Bit 0	Priority			Interrupt
				Int.	Level	Interrupt Type	Interrupt Source
								Reset Control
ID 2	ID1		ID0	Pend.
0	0		0	1	–	None	None	–
						Receiver Line	Overrun Error, Parity	Reading the LSR (Line
0	1		1	0	Highest		Error, Framing Error or
						Status		Status register)
							Break Interrupt
								Reading the RBR
0	1		0	0	Second	Received Data	Receiver Data Available	(Receiver Buffer register)
						Available	or Trigger Level Reached	or the FIFO Drops below
								the Trigger Level
							No characters have been
						Character	removed from or entered
							into the RCVR FIFO dur-	Reading the RBR
1	1		0	0	Second	Time-out	ing the last four character
								(Receiver Buffer register)
						Indication	times, and there is at least
							one character in it during
							this time
						Transmitter		Reading the IIR register (if
0	0		1	0	Third	Holding	Transmitter Holding	the source of interrupt) or
						Register	Register Empty	writing into the Transmit-
						Empty		ter Holding register
							Clear to Send,
0	0		0	0	Fourth	Modem Status	Data Set Ready,	Reading the MSR
							Ring Indicator, or Data	(Modem Status register)
							Carrier Detect
Bits 7:6		FIFOs Enable Bits–These two bits are set whenever FCR0 = 1.
Bits 5		Not used–This bit is permanently set to “0”.
Bit 4		Reserved
Bit 3		Interrupt ID Bit 2–In 16C450 mode, this bit is always a “0”.
		In FIFO mode, both this bit and bit IIR2 are set whenever a time-out interrupt is pending.
Bits 2:1		Interrupt ID Bits ID0 and ID1–These two bits are used to identify the highest-priority interrupt as shown
		in Table 10-2.

Programmer’s Guide Intel Confidential 125