Intel MD566X manual Parallel Host Interface Uart Register Bit Assignments

56K V.92 Data, Fax, and Voice Chipset

Table 10-1. Parallel Host Interface UART Register Bit Assignments

REGISTER	REGISTER				BIT NUMBER
ADDRESS	NAME	7	6	5	4	3	2	1	0
7	Scratch
	register			Scratch register (SCR)
	(SCR)
	Modem	Data	Ring	Data	Clear	Delta	Trailing	Delta	Delta
						Data	Edge of	Data	Clear
6	Status	Carrier		Set	to
			Indicator			Carrier	Ring	Set	to
	register	Detect		Ready	Send
			(RI)			Detect	Indicator	Ready	Send
	(MSR)	(DCD)		(DSR)	(CTS)
						(DDCDD)	(TERI)	(DDSR)	(DCTS)
	Line	Error in	Transmitter	Transmitter
				Holding	Break	Framing	Parity	Overrun	Data
5	Status	RCVR
			Empty	register	Interrupt	Error	Error	Error	Ready
	register	FIFO
			(TEMT)	Empty	(BI)	(FE)	(PE)	(OE)	(DR)
	(LSR)	(Note 1)
				(THRE)
4	Modem							Request	Data
	Control	0	0	0	Loop	Out 2	Out 1	to	Terminal
	register							Send	Ready
	(MCR)							(RTS)	(DTR)
	Line	Divisor			Even	Parity	Number	Word	Word
		Latch						Length	Length
3	Control		Set	Stick	Parity		of
		Access				Enable		Select	Select
	register		Break	Parity	Select		Stop bits
		bit				(PEN)		bit 1	bit 0
	(LCR)		(SBRK)	(SPAR)	(EPS)		(STB)
		(DLAB)						(WLS1)	(WLS0)
	FIFO	RCVR					XMIT	RCVR
	Control		RCVR						FIFO
2							FIFO	FIFO
	register	Trigger	Trigger	Reserved	Reserved	Reserved			Enable
							Reset	Reset
	[write only]	(MSB)	(LSB)						(FIFOE)
							(XFIFOR)	(RFIFOR)
	(FCR)
	Interrupt	FIFOs	FIFOs			Interrupt	Interrupt	Interrupt	‘0’ if
	Identity			0
2	register	Enabled	Enabled		0	ID	ID	ID	Interrupt
	[read only]	(Note 1)	(Note 1)			bit 2	bit 1	bit 0	pending
	(IIR)					(Note 1)
1	Interrupt					Modem	Receiver	Transmitter	Received
						Status	Line Status	Holding Reg.	Data
	Enable	0	0	0	0
						Interrupt	Interrupt	Empty	Available
DLAB=0	register
						Enable	Enable	Int. Enable	Int. Enable
	(IER)
						(MSIE)	(RLSIE)	(THREIE)	(RDAIE)
	Transmit
0	Holding			Transmit Holding register (THR)		[Write only]
	register
DLAB=0	[write only]
	(THR)
	Receiver
0	Buffer			Receiver Buffer register (RBR)		[Read only]
	register
DLAB=0	[read only]
	(RBR)
1	Divisor
	Latch				MS Divisor Latch (DLM)
	(MS)
DLAB=1
	(DLM)
0	Divisor
	Latch
					LS Divisor Latch (DLL)
DLAB=1	(LS)
	(DLL)

Note: These bits are always ‘0’ in 16C450 mode.

120 Intel Confidential Programmer’s Guide