Server management features are implemented using one microcontroller called the Baseboard Management Controller (BMC).
Baseboard Management Controller (BMC)
The BMC and associated circuitry are powered from 5V_Standby, which remains active when system power is switched off. The BMC is IPMI 1.0 compliant.
The primary function of the BMC is to autonomously monitor system platform management events and log their occurrence in the nonvolatile System Event Log (SEL). The BMC is compliant to the Intelligent Platform Management Interface Specification, Version 1.0. These events include overtemperature and overvoltage conditions, fan failure, or chassis intrusion. While monitoring, the BMC maintains the nonvolatile Sensor Data Record Repository (SDRR), from which
Field service personnel can retrieve SEL contents after system failure for analysis by using system management tools like Intel®LANDesk®Server Manager, Intel Server Control (ISC), or Direct Platform control (DPC). Because 5V_Standby provides power the BMC, SEL (and SDRR) information is also available via the interperipheral management bus (IPMB). During monitoring, the BMC performs the following functions:
∙Baseboard temperature and voltage monitoring
∙Processor presence monitoring and FRB control
∙Baseboard fan failure detection and indicator control
∙SEL interface management
∙Sensor Data Record Repository (SDRR) interface management
∙SDR/SEL timestamp clock
∙Baseboard Field Replaceable Unit (FRU) information interface
∙System management watchdog timer
∙SMI/NMI Status Monitor
∙Front panel NMI handling
∙Event receiver
∙IPMB Management Controller Initialization Agent
∙Secure mode control, front panel lock/unlock initiation, and video blank and diskette write protect monitoring and control
∙ACPI Support
∙Direct Platform Control (DPC) support
∙Platform Event Paging (PEP) / Platform Event Filtering (PEF)
∙Power distribution board monitoring
∙Speaker beep capability. When the system is powered up, this capability is used to indicate conditions such as "empty processor slot"
∙Pentium III Xeon processor SEEPROM interface for Processor Information ROM (PIROM) and Scratch EEPROM access
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