Maxon Telecom SP210 Pll Ic, Out-of-Lock Detector, Charge Pump and Loop Filter, DC to DC Converter

Maxon SP200/210 Radio SP200/210

In transmit the VCO has modulation from the audio processing circuitry applied to D202. C204 is used to provide compensation for non-linearity caused by the modulation diode and maintains a constant modulation regardless of the frequency of operation.

PLL IC

The reference frequency from the TCXO, at 12.8 MHz, is connected to pin 20 of IC2 (MC145191). The appropriate VCO is connected to pin 11.

The external reference frequency, TCXO input, is divided by the reference divider (REFDIV), which is set to divide by 2048 for 12.5kHz or 25kHz channels (6.25kHz) or to divide by 2560 for 20kHz channels (5kHz). This is known as the reference frequency, Fr.

The comparison frequency is determined by the settings which are stored within the EEPROM (IC404). Choice of these comparison frequencies means that the minimum step size of the synthesiser is either 5kHz or 6.25kHz and therefore, 12.5kHz, 20kHz and 25kHz channel spacings can be accommodated.

IC2 is programmed on pin 19, to obtain the desired frequency, by serial data from the microcontroller (IC403 pin 21). IC2 Pin 19 is the data input and pin 18 is the clock input and pin 17 is the PLL enable line.

The VCO frequency, Fin, is divided down by the programmable divider (64/65 prescaler VARDIV) to, again, produce 5kHz or 6.25kHz. This frequency is known as the variable frequency, Fv.

In the phase/frequency comparator, the phase difference between the reference frequency, Fr, and the VCO signal, Fv, is compared.

When Fv = Fr, the phase detector output (pins 3 and 4, IC2) produces narrow negative pulses and Fv and Fr pulse widths are identical. When Fv > Fr, pin 4 (V) pulses negative, with pin 3 (R) remaining high. When Fv < Fr, pin 3 (R) pulses negative with pin 4 (V) remaining high. The signal at pins 3 and 4 is smoothed by the loop filter and applied to the VCO.

Out-of-Lock Detector

The out-of-lock detector output remains essentially high with narrow low-going pulses when in lock. The output pulses low when Fr and Fv are out of phase or at a different frequency (results in wider pulses). These pulses at pin 2 are buffered by Q5 and then integrated by R1 and C11. The resultant voltage is fed to the microcontroller, IC403, pin 53.

IC2 has two output ports:

Port A pin 16 Configurable digital port, which is used as tx enable 2, which controls the application of volts to the PA stage.

Port B pin 15 Open drain digital output, which is used as a power save control.

Pin 13 labelled test2 allows the technician to see the output of the dual modules prescaler for trouble shooting purposes, no connection should be made to this pin.

Charge Pump and Loop Filter

Transistors Q6 to Q8 and Q11, and associated components, form the charge pump. The phase detector output from IC2 pins 3 and 4 are combined by the charge pump to produce a 0 to 12V tuning voltage.

The voltage signal is filtered by the loop filter (R12 – R14, C21 - C24) to remove harmonics of the reference frequency.

DC to DC Converter

The DC to DC converter, converts the +7.5 V to a 16 V suppy. This is used to provide the tuning voltage for the VCO. A wide voltage range is required to allow for the wideband operation of the radio.

Q904, Q905 and associated components, form a 200kHz oscillator. The output of the oscillator is rectified (voltage tripled) by D901, D902 and D903. C901, C902 and C916 provide filtering. The resultant 16Vdc is passed to R909 and then becomes the supply rail for the charge pump.

DETAILED FUNCTIONAL DESCRIPTION	Issue 1.0
Page 5-6	03/01