Chapter 3 MOTLoad Firmware
■L1 data cache has been initialized (invalidated) and is disabled.
■L2 cache is disabled.
■L3 cache is disabled.
■RAM has been initialized and is mapped starting at CPU address 0.
■If RAM ECC or parity is supported, RAM has been scrubbed of ECC or parity errors.
■The active Flash bank (boot) is mapped from the upper end of the address space.
■If specified by COPY_TO_RAM, the image has been copied to RAM at the address specified by ImageRamAddress.
■CPU register R1 (the stack pointer) has been initialized to a value near the end of RAM.
■CPU register R3 is added to the following structure:
typedef struct altBootData {
unsigned int ramSize;/* board’s RAM size in MB */ void flashPtr;/* ptr to this image in flash */ char boardType[16];/* name string, eg MVME3100 */ void globalData;/* 16K, zeroed, user defined */ unsigned int reserved[12];
} altBootData_t;
Alternate Boot Data Structure
The globalData field of the alternate boot data structure points to an area of RAM which was initialized to zeroes by the boot loader. This area of RAM is not cleared by the boot loader after execution of a POST image, or other alternate boot image, is executed. It is intended to provide a user a mechanism to pass POST image results to subsequent boot images.
The boot loader performs no other initialization of the board than that specified prior to the transfer of control to either a POST, USER, or Alternate MOTLoad image. Alternate boot images need to initialize the board to whatever state the image may further require for its execution.
POST images are expected, but not required, to return to the boot loader. Upon return, the boot loader proceeds with the scan for an executable alternate boot image. POST images that return control to the boot loader must ensure that upon return, the state of the board is consistent with the state that the board was in at POST entry. USER images should not return control to the boot loader.
MVME3100 | 33 |
