National Instruments 653X t t, t t t t, t t

Chapter 3 Timing Diagrams
© National Instruments Corporation 3-11 653X User Manual
Figure 3-8. Burst Output Timing Diagram (PCLK Reversed)
Parameter Description Minimum Maximum
Input Parameters
trs Setup time from REQ valid to PCLK 12 —
trh Hold time from PCLK to REQ invalid 0 —
Output Parameters
tpc PCLK cycle time 50 7001
tpw PCLK high pulse duration tpc/2 – 5t
pc/2 + 5
tpa PCLK to ACK valid —18
tah Hold time from PCLK to ACK invalid 3 —
tpdo PCLK to output data valid —28
tdoh Hold time from PCLK to output data
invalid
4—
tdis Setup time from input data valid to PCLK 0 —
tdih Hold time from PCLK to input data invalid 0 —
1tpc = programmable delay from 100 to 700ns, or 50 ns if programmable delay is 0. Timebase stability for the board
20MHz clock source is 50 ppm.
All timing values are in nanoseconds.
PCLK
ACK
Data Out Valid
REQ
t
rs
t
pa
t
pdo
t
pw
t
pc
t
doh
t
rh
t
ah