Chapter 3 Timing Diagrams
© National Instruments Corporation 3-17 653X User Manual
Figure 3-13. 8255 Emulation Output Timing Diagram
Parameter Description Minimum Maximum
Input Parameters
tr*r REQ low duration 75
trr* REQ high duration 75
ta*r ACK falling edge to REQ rising edge 0
tdir Input data valid to REQ rising edge 0
trdi REQ rising edge to input data invalid 10
Output Parameters
taa* ACK high duration 100
tr*a REQ falling edge to ACK rising edge 150
tdoa* Output data valid to ACK falling edge 25
trdo REQ rising edge to output data invalid 100
All timing values are in nanoseconds.
REQ
ACK
Data Out Valid
Data In Valid
tdoa*
tdir
ta*r
tr*r trr*
trdi
trdo
taa*
tr*a
ACK and REQ are shown as active low