National Instruments 653X t t, t

Chapter3 TimingDiagrams

©NationalInstruments Corporation 3-23 653XUser Manual

Figure3-19. LevelACK Output Timing Diagram

Note WithREQ edge latching disabled (default), output data valid will hold trdo ns after

the REQ edge is asserted. WithREQ edge latching enabled, that data will be held for at

most trdons after the REQ edge deasserts.

Parameter Description Minimum Maximum

InputParameters

trr* REQ pulse width 75 —

tr*r REQ inactiveduration 75 —

tar ACK to next R EQ 0 —

Output Parameters

taa* ACKpulse width 225 —

tra* REQto ACK inactive 100 200

tr*do REQ inactiveto new output data

(with REQ-edge latching)

050

trdo REQto new output data

(withREQ-edge latching disabled)

0—

tdoa Output data validto ACK

(withREQ-edge latching disabled)

251—

1tdoa(min.) = 25 + programmable delay

REQ

OutputData Valid

(REQ-edge

latching)

OutputData Valid

(REQ-edge

latchingdisabled)

tr*r

tr*do

tra*

tdoa

tar

taa*

trr*

ACK

trdo

ACKand REQ are shown as active high

Contents

Main Page Important Information Warranty Copyright Trademarks WARNING REGARDING USE OF NATIONAL INSTRUMENTS PRODUCTS Compliance FCC/Canada Radio Frequency Interference Compliance* Determining FCC Class FCC/DOC Warnings Class A European Union - Compliance to EEC Directives Conventions Contents Chapter 1 Getting Started with Your 653X Chapter 2 Using Your 653X Chapter 3 Timing Diagrams Page Getting Started with Your 653X 653X Device Overview Control Lines What You Need to Get Started Choosing Your Programming Software National Instruments Application Software NI-DAQ Driver Software Installing Your Software Unpacking Your 653XDevice Installing Your 653XDevice Installing the PCI-DIO-32HS, PCI-6534, or PCI-7030/6533 Installing the PXI-6533, PXI-6534, or PXI-7030/6533 Installing the AT-DIO-32HS Installing the DAQCard-6533 for PCMCIA Configuring the 653X In Windows In Mac OS Using Your 653X Choosing the Correct Mode for Your Application Controlling and Monitoring Static Digital LinesUnstrobed I/O Configuring Digital Lines Standard Output Wired-OR Output Using Control Lines as Extra Unstrobed Data Lines Page Programming the Control/Timing Lines as Extra Unstrobed Data Lines Transferring Data Between Two DevicesHandshaking I/O Deciding the Width of Data to Transfer Deciding Data Transfer Direction Deciding Which Handshaking Protocol to Use Using the Burst Protocol Deciding the PCLK Signal Direction Selecting ACK/REQ Signal Polarity Choosing Whether or Not to Use a Programmable Delay Continuous Output Page Choosing the Startup Sequence Using an Initialization Order Controlling Line Polarities Chapter 2 Using Your 653X Figure 2-4. Programming Buffered Handshaking I/O in NI-DAQ National Instruments Corporation 2-13 653X User Manual Figure 2-5. Programming Unbuffered Handshaking I/O in NI-DAQ Figure 2-6. Programming Handshaking Input inLabVIEW/LabVIEW RT Figure 2-7. Programming Handshaking Output in LabVIEW/LabVIEW RT Generating and Receiving Digital Patterns and Waveform sPattern I/O Deciding the Width of Data to Transfer Deciding Transfer Direction Choosing an Internal or External REQ Source Deciding the REQ Polarity Deciding the Transfer Rate Deciding How to Start and Stop Data TransferTriggering Start Trigger Stop Trigger Start and Stop Trigger Pattern-Matching Trigger (Input Only) Page Continuous Output Monitoring Data Transfer Page Figure 2-13. Programming Pattern I/O (Continuous) in NI-DAQ Figure 2-14. Programming Pattern I/O in LabVIEW/LabVIEW RT Monitoring Line StateChange Detection Deciding the Width of Data to Acquire Deciding Which Lines You Want to Monitor Deciding How to Start and Stop Data TransferTriggering Start Trigger Stop Trigger Start and Stop Trigger Pattern-Matching Trigger Page Page Chapter 2 Using Your 653X 653X User Manual 2-32 ni.com Figure 2-20. Programming Change Detection (Continuous) in NI-DAQ Specify data mask here Figure 2-21. Programming Change Detection (Single Buffer) in NI-DAQ Specify data mask here Figure 2-22. Programming Change Detection for LabVIEW/LabVIEW RT Timing Diagrams Pattern I/O Timing Diagrams Internal REQ Signal Source External REQ Signal Source t t t t t Handshaking I/O Timing Diagrams Comparing the Different Handshaking Protocols Using the Burst Protocol Page Page t t t t t t t t t t t t t t t t t t t t t t t t Using Asynchronous Protocols Using the 8255-Emulation Protocol Page Figure 3-10. 8255 Emulation Input State Machine Page Figure 3-12. 8255 Emulation Output State Machine t t t t t t t t t Using the Level-ACK Protocol Figure 3-15. Level ACK Input State Machine t t t Page Figure 3-18. Level ACK Output State Machine t t t Using Protocols Based on Signal Edges Using the Trailing-Edge Protocol Figure 3-20. Trailing Edge Input Handshaking Sequence Figure 3-21. Trailing Edge Input State Machine t Figure 3-23. Trailing Edge Output Handshaking Sequence Figure 3-24. Trailing Edge Output State Machine t t t Using the Leading-Edge Protocol Figure 3-27. Leading Edge Input State Machine t t t Page Figure 3-30. Leading Edge Output State Machine X t t Using the Long-Pulse Protocol Figure 3-33. Long Pulse Input State Machine t t * Figure 3-36. Long Pulse Output State Machine t A Specifications Digital I/O Memory Page Power Requirement Power Available at I/O Connector Physical Environment Page B Using PXI with CompactPCI C Connecting Signals with Accessories Control Signals Appendix C Connecting Signals with Accessories 653X User Manual C-2 ni.com Making 68-Pin Signal Connections Caution Do not make connections that exceed any of the maximum input or output ratings Figure C-1. 653X I/O Connector 68-Pin Assignments Signal Descriptions Table C-3. Signal Descriptions Table C-3. Signal Descriptions (Continued) Making 50-Pin Signal Connections Figure C-2. 68-to-50-Pin Adapter Pin Assignments Use TableC-4 to find the accessories designed to connect to your 653Xdevice. Optional Equipment for Connecting Signals D Hardware Considerations Figure D-1. AT-DIO-32HS Block Diagram Block Diagrams Figure D-2. DAQCard-6533 for PCMCIA Block Diagram Figure D-3. PCI-DIO-32HS, PCI/PXI-7030/6533, and PXI-6533 Block Diagram Appendix D Hardware Considerations FPGA PCI I/O Channel SCARAB Memory 1 Figure D-4. PCI/PXI-6534 Block Diagram 653X User Manual D-4 ni.com Data Lines (32) Control Lines (8) RTSI/PXI Trigger Bus Power-On State Power Connections Selecting and Terminating Cables Using the Schottky-Diode Termination Scheme Page How Much Current Can I Sink or Source? RTSI and PXI Trigger Bus Interfaces Board, RTSI, and PXI Bus Clocks RTSI and PXI Bus Triggers E Optimizing Your Transfer Rates Determining the Maximum Transfer Rates Obtaining the Fastest Transfer Rates Interpreting Benchmark Results AT-DIO-32HS PCI-DIO-32HS PXI-6533 DAQCard-6533 for PCMCIA PCI-6534 PXI-6534 PCI-7030/6533 with LabVIEW RT PXI-6533 with LabVIEW RT Page F Technical Support Resources Web Support NI Developer Zone Customer Education System Integration Worldwide Support Glossary Numbers/Symbols A B C D F Page M P R S T U V Page Index Numbers A B C D E F G H Page I L M N O P R S Page T U V