
Chapter 3 Timing Diagrams
653X User Manual 3-28 ni.com
Figure 3-25. Trailing Edge Output Timing Diagram
Note When REQ-edge latching is disabled (default), output data valid will be held
tr*do(1)ns after the trailing edge of REQ occurs. With REQ-edge latching enabled, output
data will be held at most tr*do(1) ns after the trailing edge of REQ occurs.
Parameter Description Minimum Maximum
Input Parameters
trr* REQ pulse width 75 —
tr*r REQ inactive duration 75 —
ta*r* ACK inactive to next REQ inactive 0 —
Output Parameters
taa* ACK pulse width 22512752
tr*do(1) REQ inactive to new output data
(with REQ-edge latching)
050
tr*do(2) REQ inactive to new output data
(with REQ-edge latching disabled)
0—
tdoa Output data valid to ACK
(with REQ-edge latching disabled)
25 —
1 taa* (min) = 225 + programmable delay
2 taa* (max) = 275 + programmable delay
REQ
Output Data Valid
(REQ-edge
latching)
Output Data Valid
(REQ-edge
latching disabled)
t
r*r
t
r*do(1)
t
doa
t
aa*
t
a*r*
t
rr*
ACK
t
r*do(2)
ACK and REQ are shown as active high