
Chapter 3 Timing Diagrams
653X User Manual 3-26 ni.com
Figure 3-22. Trailing Edge Input Timing Diagram
Note When REQ-edge latching is enabled (default), the REQ edge determines when data
will be latched. Input data valid needs to be held tr*di after the trailing edge of REQ occurs.
When REQ-edge latching is disabled, input data valid needs to be held tadi after the active
going edge of the ACK signal occurs.
Parameter Description Minimum Maximum
Input Parameters
trr* REQ pulse width 75 —
tr*r REQ inactive duration 75 —
tdir* Input data setup to REQ inactive
(with REQ-edge latching)
0—
tr*di Input data hold from REQ inactive
(with REQ-edge latching)
10 —
tdir Input data setup to REQ
(with REQ-edge latching disabled)
0—
tadi Input data hold from ACK
(with REQ-edge latching disabled)
0—
Output Parameters
taa* ACK pulse width 22512752
ta*r* ACK inactive to next REQ inactive 0 —
1 taa* (min.) = 225 + programmable delay
2 taa*(max) = 275 + programmable delay
REQ
Input Data Valid
(REQ-edge
latching)
Input Data Valid
(REQ-edge
latching disabled)
tdir*
tr*r
tdir
taa* ta*r*
trr*
tr*di
ACK
tadi
ACK and REQ are shown as active high