Model 3088A Series Getting Started Guide | 2 • Configuration |
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Table 2 lists the Model 3088A’s configurable parameters.
Table 2. OnSite configurable parameters
Parameter | Description | Possible Values |
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Password | The password used to login to the console. | Character strings |
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| characters long. |
Circuit ID | The circuit ID used to identify the unit. | Character string |
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| characters long. |
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DTE Loops | The | Enabled or Disabled |
(model /CA & /A) | RLAL pins. If DTE loops are disabled, requests for loopbacks on |
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| these pins will be ignored. |
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TX Clock | Defines where | Normal or Inverted |
(models /CA, /A & | pled in relation to the TX clock: on the falling edge (normal) or the |
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/D) | rising edge (inverted) of the TX clock. |
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DSL Data Rate/ | Defines the number of DSL timeslots. The DSL data rate is calculated | |
Timeslots | by the equation: data rate = DSL timeslots x 64k. This value also |
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| defines the maximum serial/E1 data rate. |
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Serial/E1 Timeslots | Defines the total number of serial/E1 timeslots utilized. This value | |
| must be less than or equal to DSL timeslots. | |
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Timeslot | Defines |
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Mapping | timeslots are mapped to the first n |
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(Model /K) | line. Line type determines which timeslots are |
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Line Type | Defines the framing format of the E1 line. | |
(Model /K) |
| (Clear Channel |
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| G.703) |
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Line Code | Selects line coding for the E1 line. | AMI |
(Model /K) |
| HDB3 (E1 only) |
Line Build Out | Selects wave form used on the E1 line. | |
(Model /K) |
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RX Equalizer | When enabled, this feature removes signal distortion introduced on | Enabled (select for |
(Model /K) | the E1 cable. | |
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| Disabled (select for |
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| haul LBO (line build- |
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| out) is defined by |
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| ANSI T1.403). |
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Introduction | 20 |