Intel 8086-1, 8086-2 manual Logic

Page 28

8086

Table 2. Instruction Set Summary (Continued)

Mnemonic and

Description

Instruction Code

LOGIC

7 6 5 4 3 2 1 0

7 6 5 4 3 2 1 0

7 6 5 4 3 2 1 0

7 6 5 4 3 2 1 0

NOT e Invert

 

 

 

 

1 1 1 1 0 1 1 w

mod 0 1 0 r/m

 

 

SHL/SAL e Shift Logical/Arithmetic Left

1 1 0 1 0 0 v w

mod 1 0 0 r/m

 

 

SHR e Shift Logical Right

1 1 0 1 0 0 v w

mod 1 0 1 r/m

 

 

SAR e Shift Arithmetic Right

1 1 0 1 0 0 v w

mod 1 1 1 r/m

 

 

ROL e Rotate Left

1 1 0 1 0 0 v w

mod 0 0 0 r/m

 

 

ROR e Rotate Right

1 1 0 1 0 0 v w

mod 0 0 1 r/m

 

 

RCL e Rotate Through Carry Flag Left

1 1 0 1 0 0 v w

mod 0 1 0 r/m

 

 

RCR e Rotate Through Carry Right

1 1 0 1 0 0 v w

mod 0 1 1 r/m

 

 

AND e And:

 

 

 

 

Reg./Memory and Register to Either

0 0 1 0 0 0 d w

mod reg r/m

 

 

 

 

 

 

 

Immediate to Register/Memory

1 0 0 0 0 0 0 w

mod 1 0 0 r/m

data

data if w e 1

 

 

 

 

 

Immediate to Accumulator

0 0 1 0 0 1 0 w

data

data if w e 1

 

TEST e And Function to Flags, No Result:

 

 

 

 

Register/Memory and Register

1 0 0 0 0 1 0 w

mod reg r/m

 

 

 

 

 

 

 

Immediate Data and Register/Memory

1 1 1 1 0 1 1 w

mod 0 0 0 r/m

data

data if w e 1

 

 

 

 

 

Immediate Data and Accumulator

1 0 1 0 1 0 0 w

data

data if w e 1

 

OR e Or:

 

 

 

 

Reg./Memory and Register to Either

0 0 0 0 1 0 d w

mod reg r/m

 

 

 

 

 

 

 

Immediate to Register/Memory

1 0 0 0 0 0 0 w

mod 0 0 1 r/m

data

data if w e 1

 

 

 

 

 

Immediate to Accumulator

0 0 0 0 1 1 0 w

data

data if w e 1

 

XOR e Exclusive or:

 

 

 

 

Reg./Memory and Register to Either

0 0 1 1 0 0 d w

mod reg r/m

 

 

 

 

 

 

 

Immediate to Register/Memory

1 0 0 0 0 0 0 w

mod 1 1 0 r/m

data

data if w e 1

 

 

 

 

 

Immediate to Accumulator

0 0 1 1 0 1 0 w

data

data if w e 1

 

STRING MANIPULATION

 

 

 

 

REP e Repeat

 

 

 

 

1 1 1 1 0 0 1 z

 

 

 

MOVS e Move Byte/Word

 

 

 

 

1 0 1 0 0 1 0 w

 

 

 

CMPS e Compare Byte/Word

 

 

 

 

1 0 1 0 0 1 1 w

 

 

 

SCAS e Scan Byte/Word

 

 

 

 

1 0 1 0 1 1 1 w

 

 

 

LODS e Load Byte/Wd to AL/AX

 

 

 

 

1 0 1 0 1 1 0 w

 

 

 

STOS e Stor Byte/Wd from AL/A

 

 

 

 

1 0 1 0 1 0 1 w

 

 

 

CONTROL TRANSFER

 

 

 

 

CALL e Call:

 

 

 

 

Direct within Segment

1 1 1 0 1 0 0 0

disp-low

disp-high

 

 

 

 

 

 

Indirect within Segment

1 1 1 1 1 1 1 1

mod 0 1 0 r/m

 

 

 

 

 

 

 

Direct Intersegment

1 0 0 1 1 0 1 0

offset-low

offset-high

 

Indirect Intersegment

seg-low

seg-high

1 1 1 1 1 1 1 1

mod 0 1 1 r/m

Mnemonics ' Intel, 1978

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Contents Pin Configuration CPU Block DiagramLOW BHE/S BHEReset ReadyIntr TestLOW HighRQ/GT0 RQ/GT1Inta ALEDT/R DENFunctional Description Minimum and Maximum Modes BUS OperationMinimum Mode 8086 Typical Configuration Read I/O Write I/OInstruction Fetch Read Data from MemoryProcessor Reset and Initialization Alternate Data extra segmentAddressing Interrupt OperationsHalt Maskable Interrupt IntrREAD/MODIFY/WRITE Semaphore Operations VIA Lock External Synchronization VIA Test System TIMING-MINIMUM SystemBUS TIMING-MEDIUM Size Systems Absolute Maximum Ratings Minimum Complexity System Timing Requirements TclclTclch TchclCharacteristics Timing ResponsesMinimum Mode Testing INPUT, Output Waveform Testing Load CircuitWaveforms Waveforms Minimum Mode Characteristics TinvchNMI, Test Tgvch TchgxTclml TclmhTryhsh TchsvTrhav TCLCL-45 TCLCL-35 TCLCL-40Tchdtl TchdthMaximum Mode Waveforms Maximum Mode Asynchronous Signal Recognition BUS Lock Signal Timing Maximum Mode Only Reset TimingREQUEST/GRANT Sequence Timing Maximum Mode only WaveformsHOLD/HOLD Acknowledge Timing Minimum Mode only Instruction Set Summary Data TransferArithmetic Logic 8086 1 reg 1 1 Data Sheet Revision ReviewBit w e Segment 000 001 010 011 100 101 110 111
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