8086
A.C. CHARACTERISTICS
MAX MODE SYSTEM (USING 8288 BUS CONTROLLER)
TIMING REQUIREMENTS
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| Min | Max | Min | Max | Min | Max |
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TCLCL | CLK Cycle Period | 200 | 500 | 100 | 500 | 125 | 500 | ns |
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TCLCH | CLK Low Time | 118 |
| 53 |
| 68 |
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TCHCL | CLK High Time | 69 |
| 39 |
| 44 |
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TCH1CH2 | CLK Rise Time |
| 10 |
| 10 |
| 10 | ns | From 1.0V to 3.5V | ||||||
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TCL2CL1 | CLK Fall Time |
| 10 |
| 10 |
| 10 | ns | From 3.5V to 1.0V | ||||||
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TDVCL | Data in Setup Time | 30 |
| 5 |
| 20 |
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TCLDX | Data in Hold Time | 10 |
| 10 |
| 10 |
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TR1VCL | RDY Setup Time | 35 |
| 35 |
| 35 |
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| into 8284A |
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| (Notes 1, 2) |
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TCLR1X | RDY Hold Time | 0 |
| 0 |
| 0 |
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| into 8284A |
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| (Notes 1, 2) |
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TRYHCH | READY Setup | 118 |
| 53 |
| 68 |
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| Time into 8086 |
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TCHRYX | READY Hold Time | 30 |
| 20 |
| 20 |
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| into 8086 |
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TRYLCL | READY Inactive to | b8 |
| b10 |
| b8 |
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| CLK (Note 4) |
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TINVCH | Setup Time for | 30 |
| 15 |
| 15 |
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| Recognition (INTR, |
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| NMI, TEST) |
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| (Note 2) |
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TGVCH | RQ/GT Setup Time | 30 |
| 15 |
| 15 |
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| (Note 5) |
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TCHGX | RQ Hold Time into | 40 |
| 20 |
| 30 |
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| 8086 |
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TILIH | Input Rise Time |
| 20 |
| 20 |
| 20 | ns | From 0.8V to 2.0V | ||||||
| (Except CLK) |
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TIHIL | Input Fall Time |
| 12 |
| 12 |
| 12 | ns | From 2.0V to 0.8V | ||||||
| (Except CLK) |
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