Intel 8086-2 Tclml, Tclmh, Tryhsh, Tchsv, Tclsh, Tclav, Tclaz, Tclax Tsvlh, Tsvmch, Tcllh

Page 20

8086

A.C. CHARACTERISTICS (Continued)

TIMING RESPONSES

Symbol

Parameter

8086

 

8086-1

8086-2

Units

Test

 

 

 

 

 

 

 

 

 

Min

 

Max

Min

Max

Min

Max

 

Conditions

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TCLML

Command Active

10

 

35

10

35

10

35

ns

 

 

Delay (See Note 1)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TCLMH

Command Inactive

10

 

35

10

35

10

35

ns

 

 

Delay (See Note 1)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TRYHSH

READY Active to

 

 

110

 

45

 

65

ns

 

 

Status Passive (See

 

 

 

 

 

 

 

 

 

 

Note 3)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TCHSV

Status Active Delay

10

 

110

10

45

10

60

ns

 

 

 

 

 

 

 

 

 

 

 

 

TCLSH

Status Inactive

10

 

130

10

55

10

70

ns

 

 

Delay

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TCLAV

Address Valid Delay

10

 

110

10

50

10

60

ns

 

 

 

 

 

 

 

 

 

 

 

 

TCLAX

Address Hold Time

10

 

 

10

 

10

 

ns

 

 

 

 

 

 

 

 

 

 

 

 

TCLAZ

Address Float Delay

TCLAX

 

80

10

40

TCLAX

50

ns

 

 

 

 

 

 

 

 

 

 

 

 

TSVLH

Status Valid to ALE

 

 

15

 

15

 

15

ns

 

 

High (See Note 1)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TSVMCH

Status Valid to

 

 

15

 

15

 

15

ns

 

 

MCE High (See

 

 

 

 

 

 

 

 

 

 

Note 1)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CL e 20 – 100 pF

TCLLH

CLK Low to ALE

 

 

15

 

15

 

15

ns

 

Valid (See Note 1)

 

 

 

 

 

 

 

 

for all 8086

 

 

 

 

 

 

 

 

 

 

Outputs (In

TCLMCH

CLK Low to MCE

 

 

15

 

15

 

15

ns

 

 

 

 

addition to 8086

 

High (See Note 1)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

self-load)

 

 

 

 

 

 

 

 

 

 

TCHLL

ALE Inactive Delay

 

 

15

 

15

 

15

ns

 

 

(See Note 1)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TCLMCL

MCE Inactive Delay

 

 

15

 

15

 

15

ns

 

 

(See Note 1)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TCLDV

Data Valid Delay

10

 

110

10

50

10

60

ns

 

 

 

 

 

 

 

 

 

 

 

 

TCHDX

Data Hold Time

10

 

 

10

 

10

 

ns

 

 

 

 

 

 

 

 

 

 

 

 

TCVNV

Control Active

5

 

45

5

45

5

45

ns

 

 

Delay (See Note 1)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TCVNX

Control Inactive

10

 

45

10

45

10

45

ns

 

 

Delay (See Note 1)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TAZRL

Address Float to

0

 

 

0

 

0

 

ns

 

 

READ Active

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TCLRL

RD Active Delay

10

 

165

10

70

10

100

ns

 

 

 

 

 

 

 

 

 

 

 

 

TCLRH

RD Inactive Delay

10

 

150

10

60

10

80

ns

 

 

 

 

 

 

 

 

 

 

 

 

20

Image 20
Contents Pin Configuration CPU Block DiagramLOW BHE/S BHEReset ReadyIntr TestLOW HighRQ/GT0 RQ/GT1Inta ALEDT/R DENFunctional Description Minimum and Maximum Modes BUS OperationMinimum Mode 8086 Typical Configuration Read I/O Write I/OInstruction Fetch Read Data from MemoryProcessor Reset and Initialization Alternate Data extra segmentAddressing Interrupt OperationsREAD/MODIFY/WRITE Semaphore Operations VIA Lock Maskable Interrupt IntrHalt External Synchronization VIA Test System TIMING-MINIMUM SystemBUS TIMING-MEDIUM Size Systems Absolute Maximum Ratings Minimum Complexity System Timing Requirements TclclTclch TchclCharacteristics Timing ResponsesWaveforms Testing INPUT, Output Waveform Testing Load CircuitMinimum Mode Waveforms Minimum Mode Characteristics TinvchNMI, Test Tgvch TchgxTclml TclmhTryhsh TchsvTrhav TCLCL-45 TCLCL-35 TCLCL-40Tchdtl TchdthMaximum Mode Waveforms Maximum Mode Asynchronous Signal Recognition BUS Lock Signal Timing Maximum Mode Only Reset TimingREQUEST/GRANT Sequence Timing Maximum Mode only WaveformsHOLD/HOLD Acknowledge Timing Minimum Mode only Instruction Set Summary Data TransferArithmetic Logic 8086 Bit w e Segment 000 001 010 011 100 101 110 111 Data Sheet Revision Review1 reg 1 1