Intel 8086-1, 8086-2 manual Arithmetic

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CWD e
CBW e
IDIV e AAD e
IMUL e
DIV e
AAM e
MUL e
DAS e
AAS e

8086

Table 2. Instruction Set Summary (Continued)

Mnemonic and

Description

Instruction Code

ARITHMETIC

ADD e Add:

Reg./Memory with Register to Either Immediate to Register/Memory Immediate to Accumulator

ADC e Add with Carry: Reg./Memory with Register to Either Immediate to Register/Memory Immediate to Accumulator

7 6 5 4 3 2 1 0

7 6 5 4 3 2 1 0

7 6 5 4 3 2 1 0

7 6 5 4 3 2 1 0

 

 

 

 

0 0 0 0 0 0 d w

mod reg r/m

 

 

 

 

 

 

1 0 0 0 0 0 s w

mod 0 0 0 r/m

data

data if s: w e 01

 

 

 

 

0 0 0 0 0 1 0 w

data

data if w e 1

 

 

 

 

 

0 0 0 1 0 0 d w

mod reg r/m

 

 

 

 

 

 

1 0 0 0 0 0 s w

mod 0 1 0 r/m

data

data if s: w e 01

 

 

 

 

0 0 0 1 0 1 0 w

data

data if w e 1

 

INC e Increment:

Register/Memory

Register

AAAe ASCII Adjust for Add

BAA e Decimal Adjust for Add SUB e Subtract:

Reg./Memory and Register to Either Immediate from Register/Memory Immediate from Accumulator

SSB e Subtract with Borrow Reg./Memory and Register to Either Immediate from Register/Memory Immediate from Accumulator

DEC e Decrement:

Register/memory

Register

NEG e Change sign CMP e Compare: Register/Memory and Register Immediate with Register/Memory Immediate with Accumulator

ASCII Adjust for Subtract

Decimal Adjust for Subtract

Multiply (Unsigned)

Integer Multiply (Signed)

ASCII Adjust for Multiply

Divide (Unsigned)

Integer Divide (Signed) ASCII Adjust for Divide Convert Byte to Word Convert Word to Double Word

1 1 1 1 1 1 1 w

mod 0 0 0 r/m

 

 

 

 

 

 

0 1 0 0 0 reg

 

 

 

 

 

 

 

0 0 1 1 0 1 1 1

 

 

 

 

 

 

 

0 0 1 0 0 1 1 1

 

 

 

 

 

 

 

0 0 1 0 1 0 d w

mod reg r/m

 

 

 

 

 

 

1 0 0 0 0 0 s w

mod 1 0 1 r/m

data

data if s w e 01

 

 

 

 

0 0 1 0 1 1 0 w

data

data if w e 1

 

 

 

 

 

0 0 0 1 1 0 d w

mod reg r/m

 

 

 

 

 

 

1 0 0 0 0 0 s w

mod 0 1 1 r/m

data

data if s w e 01

 

 

 

 

0 0 0 1 1 1 w

data

data if w e 1

 

 

 

 

 

1 1 1 1 1 1 1 w

mod 0 0 1 r/m

 

 

 

 

 

 

0 1 0 0 1 reg

 

 

 

 

 

 

 

1 1 1 1 0 1 1 w

mod 0 1 1 r/m

 

 

 

 

 

 

0 0 1 1 1 0 d w

mod reg r/m

 

 

 

 

 

 

1 0 0 0 0 0 s w

mod 1 1 1 r/m

data

data if s w e 01

 

 

 

 

0 0 1 1 1 1 0 w

data

data if w e 1

 

 

 

 

 

0 0 1 1 1 1 1 1

 

 

 

 

 

 

 

0 0 1 0 1 1 1 1

 

 

 

 

 

 

 

1 1 1 1 0 1 1 w

mod 1 0 0 r/m

 

 

 

 

 

 

1 1 1 1 0 1 1 w

mod 1 0 1 r/m

 

 

 

 

 

 

1 1 0 1 0 1 0 0

0 0 0 0 1 0 1 0

 

 

 

 

 

 

1 1 1 1 0 1 1 w

mod 1 1 0 r/m

 

 

 

 

 

 

1 1 1 1 0 1 1 w

mod 1 1 1 r/m

 

 

 

 

 

 

1 1 0 1 0 1 0 1

0 0 0 0 1 0 1 0

 

 

 

 

 

 

1 0 0 1 1 0 0 0

 

 

 

 

 

 

 

1 0 0 1 1 0 0 1

 

 

 

Mnemonics ' Intel, 1978

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Contents CPU Block Diagram Pin ConfigurationBHE LOW BHE/STest ResetReady IntrRQ/GT1 LOWHigh RQ/GT0DEN IntaALE DT/RFunctional Description BUS Operation Minimum and Maximum ModesMinimum Mode 8086 Typical Configuration Read Data from Memory Read I/OWrite I/O Instruction FetchInterrupt Operations Processor Reset and InitializationAlternate Data extra segment AddressingMaskable Interrupt Intr HaltREAD/MODIFY/WRITE Semaphore Operations VIA Lock System TIMING-MINIMUM System External Synchronization VIA TestBUS TIMING-MEDIUM Size Systems Absolute Maximum Ratings Tchcl Minimum Complexity System Timing RequirementsTclcl TclchTiming Responses CharacteristicsTesting INPUT, Output Waveform Testing Load Circuit Minimum ModeWaveforms Waveforms Minimum Mode Tchgx CharacteristicsTinvch NMI, Test TgvchTchsv TclmlTclmh TryhshTchdth TrhavTCLCL-45 TCLCL-35 TCLCL-40 TchdtlMaximum Mode Waveforms Maximum Mode Waveforms Asynchronous Signal RecognitionBUS Lock Signal Timing Maximum Mode Only Reset Timing REQUEST/GRANT Sequence Timing Maximum Mode onlyHOLD/HOLD Acknowledge Timing Minimum Mode only Data Transfer Instruction Set SummaryArithmetic Logic 8086 Data Sheet Revision Review 1 reg 1 1Bit w e Segment 000 001 010 011 100 101 110 111