Intel 8086-1, 8086-2 manual Waveforms Minimum Mode

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8086

WAVEFORMS (Continued)

MINIMUM MODE (Continued)

231455 – 14

SOFTWARE HALT—

RD, WR, INTA e VOH

DT/R e INDETERMINATE

NOTES:

1.All signals switch between VOH and VOL unless otherwise specified.

2.RDY is sampled near the end of T2, T3, TW to determine if TW machines states are to be inserted.

3.Two INTA cycles run back-to-back. The 8086 LOCAL ADDR/DATA BUS is floating during both INTA cycles. Control signals shown for second INTA cycle.

4.Signals at 8284A are shown for reference only.

5.All timing measurements are made at 1.5V unless otherwise noted.

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Contents Pin Configuration CPU Block DiagramLOW BHE/S BHEIntr ResetReady TestRQ/GT0 LOWHigh RQ/GT1DT/R IntaALE DENFunctional Description Minimum and Maximum Modes BUS OperationMinimum Mode 8086 Typical Configuration Instruction Fetch Read I/OWrite I/O Read Data from MemoryAddressing Processor Reset and InitializationAlternate Data extra segment Interrupt OperationsMaskable Interrupt Intr HaltREAD/MODIFY/WRITE Semaphore Operations VIA Lock External Synchronization VIA Test System TIMING-MINIMUM SystemBUS TIMING-MEDIUM Size Systems Absolute Maximum Ratings Tclch Minimum Complexity System Timing RequirementsTclcl TchclCharacteristics Timing ResponsesTesting INPUT, Output Waveform Testing Load Circuit Minimum ModeWaveforms Waveforms Minimum Mode NMI, Test Tgvch CharacteristicsTinvch TchgxTryhsh TclmlTclmh TchsvTchdtl TrhavTCLCL-45 TCLCL-35 TCLCL-40 TchdthMaximum Mode Waveforms Maximum Mode REQUEST/GRANT Sequence Timing Maximum Mode only Asynchronous Signal RecognitionBUS Lock Signal Timing Maximum Mode Only Reset Timing WaveformsHOLD/HOLD Acknowledge Timing Minimum Mode only Instruction Set Summary Data TransferArithmetic Logic 8086 Data Sheet Revision Review 1 reg 1 1Bit w e Segment 000 001 010 011 100 101 110 111