| 1: IRQ when FIFO is half full |
ISC1: | IRQ1 signal select |
0:IRQ every Timer tick
1:IRQ when ExtTrg signal changes from ‘H’ to ‘L’
FFEN: FIFO enable pin
0:FIFO Enable (Power On Default value)
1:FIFO Disable
(To reset FIFO, set FFEN sequence as 0
3.11Hardware Interrupt Clear Register
Because of the PCI interrupt signal is level trigger, the interrupt clear register must be written to clear the flag after processing the interrupt request event, otherwise another interrupt request will be inserted and cause the software hangs on processing the interrupt event.
Address: BASE + 48h
Attribute: write only
Data Format:
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
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BASE+48h | X | X | X | X | X | X | X | X |
3.12A/D Mode & Interrupt Control Read Back Register
The AD mode setting and interrupt control setting can be read from this register. Refer to section 3.8 and section 3.10 for the detailed definition of each bit.
Address: BASE + 0Ah
Attribute: read only
Data Format:
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
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BASE+0Ah | 0 | FFEN | ISC1 | ISC0 | PTRG | EITS | TPST | ASCAN |
BASE+0Bh | X | X | X | X | X | X | X | X |
