HP NuDAQ I-9111DG/HR manual Pacer Trigger Source, Pre-Trigger Counter, 4 I/O Address

4.6.2Pacer Trigger Source

The timer #1 and timer #2 are cascaded together to generate the timer pacer trigger of A/D conversion. The frequency of the pacer trigger is software controllable. The maximum pacer signal rate is 2MHz/4=500K which excess the maximum A/D conversion rate of the PCI-9111. The minimum signal rate is 2MHz/65535/65535, which is a very slow frequency that user may never use it. The output of the programmable timer can be used as pacer interrupt source or the timer pacer trigger source of A/D conversion. In software library, the timer #1 and #2 are always set as mode 3 (rate generator).

4.6.3Pre-Trigger Counter

The timer #0 is used as the pre-trigger counter. The clock source of counter 0 is from A/D trigger source so that 8254 can count the A/D trigger numbers after the pre-trigger signal (pin-12 of CN3) is inserted. The gate control is set when the pre-trigger signal is change from ‘H’ to ‘L’, and cleared when the counter is counting down to zero. In software library, the timer #0 is always set as mode 0 (event counter).

4.6.4I/O Address

The 8254 in the PCI-9111 occupy 4 I/O address as shown below.

BASE + 40 h	LSB OR MSB OF COUNTER 0
BASE + 42 h	LSB OR MSB OF COUNTER 1
BASE + 44 h	LSB OR MSB OF COUNTER 2
BASE + 46 h	CONTROL BYTE

The programming of 8254 is controlled by the registers BASE+0 to BASE+3. Users can refer to 82C54 data sheet for the descriptions about all the features of 82C54. You can download the data sheet on the following web site:

“http://support.intel.com/support/controllers/peripheral/231164.htm”

or “http://www.tundra.com/”

Operation Theorem ∙35