I/O Address Map, A/D Data Registers | HP NuDAQ I-9111DG/HR guide

Please do not try to modify the base address and interrupt which assigned by the PCI PnP BIOS, it may cause resource confliction in your system.

3.2I/O Address Map

Most of the PCI-9111 registers are 16 bits. The users can access these registers by 16 bits I/O instructions. The following table shows the registers map, including descriptions and their offset addresses relative to the base address.

I/O Address	Write	Read

Base + 00h	DA value	AD FIFO value
Base + 02h	Digital Output	Digital Input
Base + 04h	Extended DO	Extended DI
Base + 06h	AD channel control	AD channel read back
Base + 08h	AD range control	AD range and AD status
		read back
Base + 0Ah	AD trigger mode	AD mode and interrupt
		setting read back
Base + 0Ch	Interrupt control	(Not used)
Base + 0Eh	Software AD trigger	(Not used)
Base + 10h ~3Eh	Reserved
Base + 40h	Timer 8254 Ch#0
Base + 42h	Timer 8254 Ch#1
Base + 44h	Timer 8254 Ch#2
Base + 46h	Timer Control	Timer Status
Base + 48h	Clear H/W IRQ	(Not used)

Table 3.1 I/O Address

3.3A/D Data Registers

The PCI-9111 A/D data is stored in the FIFO after conversion. The data can be transferred to host memory by software only. The register format for 12 bits PCI-9111DG and 16 bits PCI-9111HR is bit-wise alignment but not fully compatible. For 12 bits PCI-9111 data, the 4 LSBs are used to memorize the channel number in which the AD data is stored.

14 ∙ Registers Format

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HP NuDAQ I-9111DG/HR manual I/O Address Map, A/D Data Registers, Address Write Read

Contents

NuDAQ Trademarks Getting service from Adlink QuestionsPage Features Applications Specifications Software Supporting B l e o f C o n t e n t sPCI PnP Registers Address Map Libraries Installation Programming Guide Hardware Interrupt Clear RegisterConversion Interrupt Control Table of Contents ∙ What do you need VR Assignment Adjustment 9111util How to Use This Guide Page Features Introduction Specifications Applications Unipolar 0~10V Bipolar -10V~+10V Software Supporting Programming Library PCIS-LVIEW LabVIEW Driver PCIS-VEE HP-VEE DriverDAQBenchTM ActiveX Controls DASYLabTM PRO PCIS-ICL InControlTM Driver PCIS-OPC OPC Server Installation ∙ Software Installation GuideWhat You Have Unpacking PCI-9111s Layout PCB Layout of the PCI-9111 Hardware Installation Outline Jumper Descriptions Device Installation for Windows Systems Connectors Pin Assignment∙ CN 1 Digital Signal Input DI 0 ~ ∙ CN 2 Digital Signal Output do 0 ~ ∙ CN 3 Analog Input/Output, Extended I/O, Trigger Signals Daughter Board Connection Connect with ACLD-8125Connect with ACLD-9137 Connect with ACLD-9182 Registers Format PCI PnP Registers I/O Address Map A/D Data RegistersAddress Write Read I/O Address A/D Channel Control Register Address Base + 0h Attribute read only Data FormatBit Address Base + 6h Attribute write only Data Format Bit A/D Input Signal Range Control Register A/D Channel Read Back RegisterAddress Base + 6h Attribute read only Data Format Bit Address Base + 8h Attribute write only Data Format Bit A/D Trigger Mode Control Register A/D Range and Status Read back RegisterAddress Base + 8h Attribute read only Data Format Bit Address Base + 0Ah Attribute write only Data Format Bit Mode Description Address Base + 0Eh Attribute write only Data Format BitAddress Base + 0Ch Attribute write only Data Format Bit 12 A/D Mode & Interrupt Control Read Back Register Hardware Interrupt Clear RegisterAddress Base + 48h Attribute write only Data Format Bit Address Base + 0Ah Attribute read only Data Format Bit Address Base + 4h Attribute write only Data Format Bit Address Base + 4h Attribute read only Data Format BitAddress Base + 2h Attribute read only Data Format 15 D/A Output Register Address Base + 2h Attribute write only Data Format BitAddress Base + 40h ~ Base + 46h Operation Theorem A/D Conversion 1 A/D Conversion Procedure 2 A/D Signal Source Control Analog Input Signal Connection Signal Range 3 A/D Trigger Source Control 4 A/D Data Transfer Modes External Trigger EITS=1, TPST=don‘t care Fifo Half-Full Polling Pre-Trigger Control EOC Interrupt Transfer Time 6 A/D Data Format FFF IRQ Level Setting Interrupt Control System ArchitectureDual Interrupt System Interrupt Source Control Extended Digital I/O Port D/A Conversion 44mV 88mV Timer/Counter Operation Introduction Digital Input and Output Pacer Trigger Source Pre-Trigger Counter4 I/O Address Libraries Installation ++ Library Programming Guide Naming Convention Data Types 9111Initial 9111DO++ DOS ++ Windows 9111DOChannel 9111DI 9111DIChannel 9111EDI 9111EDO 10 9111EDOReadBack 11 9111SetEDOFunction 12 9111DA 13 9111ADReadData 14 9111ADReadDataRepeat 15 9111ADSetChannel 16 9111ADGetChannel 17 9111ADSetRange Input Range Gain Gain Code 18 9111ADGetRange 19 9111ADGetStatus 20 9111ADSetMode 21 9111ADGetMode 22 9111INTSetReg 24 9111ResetFIFO 23 9111INTGetReg 25 9111ADSoftTrigger 26 9111Set8254 28 9111ADTimer 27 9111Get8254 29 9111CounterStart 30 9111CounterRead 31 9111CounterStop 32 9111INTSourceControl 33 9111CLRIRQ 34 9111GetIRQChannel 35 9111GetIRQStatus 36 9111ADFFHFPolling 37 9111ADAquire 38 9111ADHRAquire 39 9111ADINTStart 40 9111ADFFHFINTStart ++ Library ∙61 41 9111ADINTStatus 42 9111ADFFHFINTStatus 43 9111ADFFHFINTRestart 44 9111ADINTStop Calibration What do you need A/D Adjustment VR AssignmentFunctions of VRs D/A Adjustment Unipolar Analog Output Bipolar Analog Output Software Utility 9111utilRunning 9111util.exe System Configuration Calibration Functional Testing Function Testing Menu Window Ieeprom Product Warranty/Service