HP NuDAQ I-9111DG/HR manual 3 A/D Trigger Source Control, Signal Range

Signal Range

The proper signal range is important for data acquisition. The input signal may be saturated if the A/D gain is too large. Sometimes, the resolution may be not enough if the signal is small. The maximum A/D signal range of PCI-9111 is +/- 10 volts when the A/D gain value is 1. The A/D gain control register controls the maximum signal input range. The signal gain is programmable with 5 levels (1, 2, 4, 8, 16). The signal range of the 16 channels will be identical all the time even if the channel number is scanning.

The available signal polarity on PCI-9111 is bi-polar but no uni-polar configuration. However, the bi-polar input range still covers the uni-polar applications. In addition the high resolution of the PCI-9111HR can cover the normal industry applications. Therefore, PCI-9111 is suitable for full range of applications.

4.1.3A/D Trigger Source Control

The A/D conversion is starting by a trigger source, and then the A/D converter will start to convert the signal to a digital value. In the PCI-9111, A/D conversion can be triggered by the Internal or External trigger source. The EITS bit of A/D control register is used to handle the internal or external trigger, please refer to section 3.8 for details. Whenever the external source is set, the internal sources are disabled.

If the internal trigger is selected, two internal sources can be selected: the software trigger or the timer pacer trigger. The A/D operation mode is controlled by A/D mode bits (EITS, TPST) of A/D mode register. Total three trigger sources are provided in the PCI-9111. The different trigger conditions are specified as follows:

Software trigger (EITS=0, TPST=0)

The trigger source is software controllable in this mode. That is, the A/D conversion is starting when any value is written into the software trigger register. This trigger mode is suitable for low speed A/D conversion. Under this mode, the timing of the A/D conversion is fully controlled by software. However, it is difficult to control the fixed A/D conversion rate unless another timer interrupt service routine is used to generate a fixed rate trigger. Refer to interrupt control section for fixed rate timer interrupt.

Timer Pacer Trigger (EITS=0, TPST=1)

An on-board timer / counter chip 8254 is used to provide a trigger source for A/D conversion at a fixed rate. Two counters of the 8254 chip are cascaded together to generate trigger pulse with precise period. Please

Operation Theorem ∙25