Intel 8086-1, 8086-2 manual Minimum and Maximum Modes, BUS Operation

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Figure 3a. Memory Organization

In referencing word data the BIU requires one or two memory cycles depending on whether or not the starting byte of the word is on an even or odd ad- dress, respectively. Consequently, in referencing word operands performance can be optimized by lo- cating data on even address boundaries. This is an especially useful technique for using the stack, since odd address references to the stack may adversely affect the context switching time for interrupt pro- cessing or task multiplexing.

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Figure 3b. Reserved Memory Locations

Certain locations in memory are reserved for specific CPU operations (see Figure 3b). Locations from

8086

address FFFF0H through FFFFFH are reserved for operations including a jump to the initial program loading routine. Following RESET, the CPU will al- ways begin execution at location FFFF0H where the jump must be. Locations 00000H through 003FFH are reserved for interrupt operations. Each of the 256 possible interrupt types has its service routine pointed to by a 4-byte pointer element consisting of a 16-bit segment address and a 16-bit offset ad- dress. The pointer elements are assumed to have been stored at the respective places in reserved memory prior to occurrence of interrupts.

MINIMUM AND MAXIMUM MODES

The requirements for supporting minimum and maxi- mum 8086 systems are sufficiently different that they cannot be done efficiently with 40 uniquely de- fined pins. Consequently, the 8086 is equipped with a strap pin (MN/MX) which defines the system con- figuration. The definition of a certain subset of the pins changes dependent on the condition of the strap pin. When MN/MX pin is strapped to GND, the 8086 treats pins 24 through 31 in maximum mode. An 8288 bus controller interprets status information coded into S0, S2, S2 to generate bus timing and control signals compatible with the MULTIBUS ar- chitecture. When the MN/MX pin is strapped to VCC, the 8086 generates bus control signals itself on pins 24 through 31, as shown in parentheses in Figure 2. Examples of minimum mode and maximum mode systems are shown in Figure 4.

BUS OPERATION

The 8086 has a combined address and data bus commonly referred to as a time multiplexed bus. This technique provides the most efficient use of pins on the processor while permitting the use of a standard 40-lead package. This ‘‘local bus’’ can be buffered directly and used throughout the system with address latching provided on memory and I/O modules. In addition, the bus can also be demulti- plexed at the processor with a single set of address latches if a standard non-multiplexed bus is desired for the system.

Each processor bus cycle consists of at least four CLK cycles. These are referred to as T1, T2, T3 and T4 (see Figure 5). The address is emitted from the processor during T1 and data transfer occurs on the bus during T3 and T4. T2 is used primarily for chang- ing the direction of the bus during read operations. In the event that a ‘‘NOT READY’’ indication is given by the addressed device, ‘‘Wait’’ states (TW) are in- serted between T3 and T4. Each inserted ‘‘Wait’’ state is of the same duration as a CLK cycle. Periods

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Contents CPU Block Diagram Pin ConfigurationBHE LOW BHE/STest ResetReady Intr RQ/GT1 LOW High RQ/GT0DEN IntaALE DT/RFunctional Description BUS Operation Minimum and Maximum ModesMinimum Mode 8086 Typical Configuration Read Data from Memory Read I/OWrite I/O Instruction FetchInterrupt Operations Processor Reset and InitializationAlternate Data extra segment AddressingHalt Maskable Interrupt IntrREAD/MODIFY/WRITE Semaphore Operations VIA Lock System TIMING-MINIMUM System External Synchronization VIA TestBUS TIMING-MEDIUM Size Systems Absolute Maximum Ratings Tchcl Minimum Complexity System Timing RequirementsTclcl TclchTiming Responses CharacteristicsMinimum Mode Testing INPUT, Output Waveform Testing Load CircuitWaveforms Waveforms Minimum Mode Tchgx CharacteristicsTinvch NMI, Test TgvchTchsv TclmlTclmh TryhshTchdth TrhavTCLCL-45 TCLCL-35 TCLCL-40 TchdtlMaximum Mode Waveforms Maximum Mode Waveforms Asynchronous Signal RecognitionBUS Lock Signal Timing Maximum Mode Only Reset Timing REQUEST/GRANT Sequence Timing Maximum Mode onlyHOLD/HOLD Acknowledge Timing Minimum Mode only Data Transfer Instruction Set SummaryArithmetic Logic 8086 1 reg 1 1 Data Sheet Revision ReviewBit w e Segment 000 001 010 011 100 101 110 111
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