Intel 8086-2, 8086-1 manual Instruction Set Summary, Data Transfer

Page 26

8086

Table 2. Instruction Set Summary

Mnemonic and

Description

Instruction Code

DATA TRANSFER

 

 

 

 

MOV e Move:

7 6 5 4 3 2 1 0

7 6 5 4 3 2 1 0

7 6 5 4 3 2 1 0

7 6 5 4 3 2 1 0

Register/Memory to/from Register

1 0 0 0 1 0 d w

mod reg r/m

 

 

 

 

 

 

 

Immediate to Register/Memory

1 1 0 0 0 1 1 w

mod 0 0 0 r/m

data

data if w e 1

 

 

 

 

 

Immediate to Register

1 0 1 1 w reg

data

data if w e 1

 

 

 

 

 

 

Memory to Accumulator

1 0 1 0 0 0 0 w

addr-low

addr-high

 

 

 

 

 

 

Accumulator to Memory

1 0 1 0 0 0 1 w

addr-low

addr-high

 

 

 

 

 

 

Register/Memory to Segment Register

1 0 0 0 1 1 1 0

mod 0 reg r/m

 

 

 

 

 

 

 

Segment Register to Register/Memory

1 0 0 0 1 1 0 0

mod 0 reg r/m

 

 

PUSH e Push:

 

 

 

 

Register/Memory

1 1 1 1 1 1 1 1

mod 1 1 0 r/m

 

 

 

 

 

 

 

Register

0 1 0 1 0 reg

 

 

 

 

 

 

 

 

Segment Register

0 0 0 reg 1 1 0

 

 

 

POP e Pop:

 

 

 

 

Register/Memory

1 0 0 0 1 1 1 1

mod 0 0 0 r/m

 

 

 

 

 

 

 

Register

0 1 0 1 1 reg

 

 

 

 

 

 

 

 

Segment Register

0 0 0 reg 1 1 1

 

 

 

XCHG e Exchange:

 

 

 

 

Register/Memory with Register

1 0 0 0 0 1 1 w

mod reg r/m

 

 

 

 

 

 

 

Register with Accumulator

1 0 0 1 0 reg

 

 

 

IN e Input from:

 

 

 

 

Fixed Port

1 1 1 0 0 1 0 w

port

 

 

 

 

 

 

 

Variable Port

1 1 1 0 1 1 0 w

 

 

 

OUT e Output to:

 

 

 

 

Fixed Port

1 1 1 0 0 1 1 w

port

 

 

 

 

 

 

 

Variable Port

1 1 1 0 1 1 1 w

 

 

 

XLAT e Translate Byte to AL

 

 

 

 

1 1 0 1 0 1 1 1

 

 

 

LEA e Load EA to Register

1 0 0 0 1 1 0 1

mod reg r/m

 

 

LDS e Load Pointer to DS

1 1 0 0 0 1 0 1

mod reg r/m

 

 

LES e Load Pointer to ES

1 1 0 0 0 1 0 0

mod reg r/m

 

 

LAHF e Load AH with Flags

1 0 0 1 1 1 1 1

 

 

 

SAHF e Store AH into Flags

1 0 0 1 1 1 1 0

 

 

 

PUSHF e Push Flags

1 0 0 1 1 1 0 0

 

 

 

POPF e Pop Flags

1 0 0 1 1 1 0 1

 

 

 

Mnemonics ' Intel, 1978

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Contents Pin Configuration CPU Block DiagramLOW BHE/S BHEIntr ResetReady TestRQ/GT0 LOWHigh RQ/GT1DT/R IntaALE DENFunctional Description Minimum and Maximum Modes BUS OperationMinimum Mode 8086 Typical Configuration Instruction Fetch Read I/OWrite I/O Read Data from MemoryAddressing Processor Reset and InitializationAlternate Data extra segment Interrupt OperationsREAD/MODIFY/WRITE Semaphore Operations VIA Lock Maskable Interrupt IntrHalt External Synchronization VIA Test System TIMING-MINIMUM SystemBUS TIMING-MEDIUM Size Systems Absolute Maximum Ratings Tclch Minimum Complexity System Timing RequirementsTclcl TchclCharacteristics Timing ResponsesWaveforms Testing INPUT, Output Waveform Testing Load CircuitMinimum Mode Waveforms Minimum Mode NMI, Test Tgvch CharacteristicsTinvch TchgxTryhsh TclmlTclmh TchsvTchdtl TrhavTCLCL-45 TCLCL-35 TCLCL-40 TchdthMaximum Mode Waveforms Maximum Mode REQUEST/GRANT Sequence Timing Maximum Mode only Asynchronous Signal RecognitionBUS Lock Signal Timing Maximum Mode Only Reset Timing WaveformsHOLD/HOLD Acknowledge Timing Minimum Mode only Instruction Set Summary Data TransferArithmetic Logic 8086 Bit w e Segment 000 001 010 011 100 101 110 111 Data Sheet Revision Review1 reg 1 1