Intel 8086-2, 8086-1 manual Minimum Mode 8086 Typical Configuration

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8086

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Figure 4a. Minimum Mode 8086 Typical Configuration

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Figure 4b. Maximum Mode 8086 Typical Configuration

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Contents Pin Configuration CPU Block DiagramLOW BHE/S BHEReset ReadyIntr TestLOW HighRQ/GT0 RQ/GT1 Inta ALE DT/R DENFunctional Description Minimum and Maximum Modes BUS OperationMinimum Mode 8086 Typical Configuration Read I/O Write I/OInstruction Fetch Read Data from MemoryProcessor Reset and Initialization Alternate Data extra segmentAddressing Interrupt OperationsREAD/MODIFY/WRITE Semaphore Operations VIA Lock Maskable Interrupt IntrHalt External Synchronization VIA Test System TIMING-MINIMUM SystemBUS TIMING-MEDIUM Size Systems Absolute Maximum Ratings Minimum Complexity System Timing Requirements TclclTclch TchclCharacteristics Timing ResponsesWaveforms Testing INPUT, Output Waveform Testing Load CircuitMinimum Mode Waveforms Minimum Mode Characteristics TinvchNMI, Test Tgvch TchgxTclml TclmhTryhsh TchsvTrhav TCLCL-45 TCLCL-35 TCLCL-40Tchdtl TchdthMaximum Mode Waveforms Maximum Mode Asynchronous Signal Recognition BUS Lock Signal Timing Maximum Mode Only Reset TimingREQUEST/GRANT Sequence Timing Maximum Mode only WaveformsHOLD/HOLD Acknowledge Timing Minimum Mode only Instruction Set Summary Data TransferArithmetic Logic 8086 Bit w e Segment 000 001 010 011 100 101 110 111 Data Sheet Revision Review1 reg 1 1