Intel 8086-1, 8086-2 manual Pin Configuration, CPU Block Diagram

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8086

16-BIT HMOS MICROPROCESSOR

8086/8086-2/8086-1

YDirect Addressing Capability 1 MByte of Memory

YArchitecture Designed for Powerful Assembly Language and Efficient High Level Languages

Y14 Word, by 16-Bit Register Set with Symmetrical Operations

Y24 Operand Addressing Modes

YBit, Byte, Word, and Block Operations

Y8 and 16-Bit Signed and Unsigned Arithmetic in Binary or Decimal Including Multiply and Divide

YRange of Clock Rates: 5 MHz for 8086,

8 MHz for 8086-2,

10 MHz for 8086-1

YMULTIBUS System Compatible Interface

YAvailable in EXPRESS

—Standard Temperature Range

—Extended Temperature Range

YAvailable in 40-Lead Cerdip and Plastic

Package

(See Packaging Spec. Order Ý231369)

The Intel 8086 high performance 16-bit CPU is available in three clock rates: 5, 8 and 10 MHz. The CPU is implemented in N-Channel, depletion load, silicon gate technology (HMOS-III), and packaged in a 40-pin CERDIP or plastic package. The 8086 operates in both single processor and multiple processor configurations to achieve high performance levels.

231455 – 2

40 Lead

Figure 2. 8086 Pin

Configuration

Figure 1. 8086 CPU Block Diagram

231455 – 1

 

September 1990

Order Number: 231455-005

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Contents CPU Block Diagram Pin ConfigurationBHE LOW BHE/SReady ResetIntr TestHigh LOWRQ/GT0 RQ/GT1ALE IntaDT/R DENFunctional Description BUS Operation Minimum and Maximum ModesMinimum Mode 8086 Typical Configuration Write I/O Read I/OInstruction Fetch Read Data from MemoryAlternate Data extra segment Processor Reset and InitializationAddressing Interrupt OperationsHalt Maskable Interrupt IntrREAD/MODIFY/WRITE Semaphore Operations VIA Lock System TIMING-MINIMUM System External Synchronization VIA TestBUS TIMING-MEDIUM Size Systems Absolute Maximum Ratings Tclcl Minimum Complexity System Timing RequirementsTclch TchclTiming Responses CharacteristicsMinimum Mode Testing INPUT, Output Waveform Testing Load CircuitWaveforms Waveforms Minimum Mode Tinvch CharacteristicsNMI, Test Tgvch TchgxTclmh TclmlTryhsh TchsvTCLCL-45 TCLCL-35 TCLCL-40 TrhavTchdtl TchdthMaximum Mode Waveforms Maximum Mode BUS Lock Signal Timing Maximum Mode Only Reset Timing Asynchronous Signal RecognitionREQUEST/GRANT Sequence Timing Maximum Mode only WaveformsHOLD/HOLD Acknowledge Timing Minimum Mode only Data Transfer Instruction Set SummaryArithmetic Logic 8086 1 reg 1 1 Data Sheet Revision ReviewBit w e Segment 000 001 010 011 100 101 110 111
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