Intel 8086-1, 8086-2 manual Waveforms, Asynchronous Signal Recognition

Page 24

8086

WAVEFORMS (Continued)

ASYNCHRONOUS SIGNAL RECOGNITION

231455 – 17

NOTE:

1. Setup requirements for asynchronous signals only to guarantee recognition at next CLK.

BUS LOCK SIGNAL TIMING (MAXIMUM MODE
ONLY)	RESET TIMING

231455 – 18

231455 – 19

REQUEST/GRANT SEQUENCE TIMING (MAXIMUM MODE ONLY)

231455 – 20

NOTE:

The coprocessor may not drive the buses outside the region shown without risking contention.

24

Image 24

Contents Pin Configuration CPU Block DiagramLOW BHE/S BHEReset ReadyIntr TestLOW HighRQ/GT0 RQ/GT1Inta ALEDT/R DENFunctional Description Minimum and Maximum Modes BUS OperationMinimum Mode 8086 Typical Configuration Read I/O Write I/OInstruction Fetch Read Data from MemoryProcessor Reset and Initialization Alternate Data extra segmentAddressing Interrupt OperationsMaskable Interrupt Intr HaltREAD/MODIFY/WRITE Semaphore Operations VIA Lock External Synchronization VIA Test System TIMING-MINIMUM SystemBUS TIMING-MEDIUM Size Systems Absolute Maximum Ratings Minimum Complexity System Timing Requirements TclclTclch TchclCharacteristics Timing ResponsesTesting INPUT, Output Waveform Testing Load Circuit Minimum ModeWaveforms Waveforms Minimum Mode Characteristics TinvchNMI, Test Tgvch TchgxTclml TclmhTryhsh TchsvTrhav TCLCL-45 TCLCL-35 TCLCL-40Tchdtl TchdthMaximum Mode Waveforms Maximum Mode Asynchronous Signal Recognition BUS Lock Signal Timing Maximum Mode Only Reset TimingREQUEST/GRANT Sequence Timing Maximum Mode only WaveformsHOLD/HOLD Acknowledge Timing Minimum Mode only Instruction Set Summary Data TransferArithmetic Logic 8086 Data Sheet Revision Review 1 reg 1 1Bit w e Segment 000 001 010 011 100 101 110 111