Intel 8086-1 Data Sheet Revision Review, reg 1 1, Bit w e Segment 000 001 010 011 100 101 110 111

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8086

Table 2. Instruction Set Summary (Continued)

Mnemonic and

Instruction Code

Description

 

 

7 6 5 4 3 2 1 0

7 6 5 4 3 2 1 0

PROCESSOR CONTROL

 

 

CLC e Clear Carry

 

 

1 1 1 1 1 0 0 0

 

CMC e Complement Carry

 

 

1 1 1 1 0 1 0 1

 

STC e Set Carry

 

 

1 1 1 1 1 0 0 1

 

CLD e Clear Direction

 

 

1 1 1 1 1 1 0 0

 

STD e Set Direction

 

 

1 1 1 1 1 1 0 1

 

CLI e Clear Interrupt

1 1 1 1 1 0 1 0

 

STI e Set Interrupt

 

 

1 1 1 1 1 0 1 1

 

HLT e Halt

 

 

1 1 1 1 0 1 0 0

 

WAIT e Wait

 

 

1 0 0 1 1 0 1 1

 

ESC e Escape (to External Device)

 

 

1 1 0 1 1 x x x

mod x x x r/m

LOCK e Bus Lock Prefix

 

 

1 1 1 1 0 0 0 0

 

NOTES:

AL e 8-bit accumulator AX e 16-bit accumulator CX e Count register DS e Data segment ES e Extra segment

Above/below refers to unsigned value Greater e more positive;

Less e less positive (more negative) signed values if d e 1 then ‘‘to’’ reg; if d e 0 then ‘‘from’’ reg

if w e 1 then word instruction; if w e 0 then byte instruc- tion

if mod e 11 then r/m is treated as a REG field

if mod e 00 then DISP e 0*, disp-low and disp-high are absent

if mod e 01 then DISP e disp-low sign-extended to 16 bits, disp-high is absent

if mod e 10 then DISP e disp-high; disp-low if r/m e 000 then EA e (BX) a (SI) a DISP if r/m e 001 then EA e (BX) a (DI) a DISP if r/m e 010 then EA e (BP) a (SI) a DISP if r/m e 011 then EA e (BP) a (DI) a DISP if r/m e 100 then EA e (SI) a DISP

if r/m e 101 then EA e (DI) a DISP if r/m e 110 then EA e (BP) a DISP* if r/m e 111 then EA e (BX) a DISP

DISP follows 2nd byte of instruction (before data if re- quired)

*except if mod e 00 and r/m e 110 then EA e disp-high; disp-low.

Mnemonics ' Intel, 1978

if s w e 01 then 16 bits of immediate data form the oper- and

if s w e 11 then an immediate data byte is sign extended to form the 16-bit operand

if v e 0 then ‘‘count’’ e 1; if v e 1 then ‘‘count’’ in (CL) x e don’t care

z is used for string primitives for comparison with ZF FLAG SEGMENT OVERRIDE PREFIX

0 0 1 reg 1 1 0

REG is assigned according to the following table:

16-Bit (w e 1)

8-Bit (w e 0)

Segment

000

AX

000

AL

00

ES

001

CX

001

CL

01

CS

010

DX

010

DL

10

SS

011

BX

011

BL

11

DS

100

SP

100

AH

 

 

101

BP

101

CH

 

 

110

SI

110

DH

 

 

111

DI

111

BH

 

 

 

 

 

 

 

 

Instructions which reference the flag register file as a 16-bit object use the symbol FLAGS to represent the file:

FLAGS e X:X:X:X:(OF):(DF):(IF):(TF):(SF):(ZF):X:(AF):X:(PF):X:(CF)

DATA SHEET REVISION REVIEW

The following list represents key differences between this and the -004 data sheet. Please review this summa- ry carefully.

1.The Intel 8086 implementation technology (HMOS) has been changed to (HMOS-III).

2.Delete all ‘‘changes from 1985 Handbook Specification’’ sentences.

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Contents Pin Configuration CPU Block DiagramLOW BHE/S BHEIntr ResetReady TestRQ/GT0 LOWHigh RQ/GT1DT/R IntaALE DENFunctional Description Minimum and Maximum Modes BUS OperationMinimum Mode 8086 Typical Configuration Instruction Fetch Read I/OWrite I/O Read Data from MemoryAddressing Processor Reset and InitializationAlternate Data extra segment Interrupt OperationsMaskable Interrupt Intr HaltREAD/MODIFY/WRITE Semaphore Operations VIA Lock External Synchronization VIA Test System TIMING-MINIMUM SystemBUS TIMING-MEDIUM Size Systems Absolute Maximum Ratings Tclch Minimum Complexity System Timing RequirementsTclcl TchclCharacteristics Timing ResponsesTesting INPUT, Output Waveform Testing Load Circuit Minimum ModeWaveforms Waveforms Minimum Mode NMI, Test Tgvch CharacteristicsTinvch TchgxTryhsh TclmlTclmh TchsvTchdtl TrhavTCLCL-45 TCLCL-35 TCLCL-40 TchdthMaximum Mode Waveforms Maximum Mode REQUEST/GRANT Sequence Timing Maximum Mode only Asynchronous Signal RecognitionBUS Lock Signal Timing Maximum Mode Only Reset Timing WaveformsHOLD/HOLD Acknowledge Timing Minimum Mode only Instruction Set Summary Data TransferArithmetic Logic 8086 Data Sheet Revision Review 1 reg 1 1Bit w e Segment 000 001 010 011 100 101 110 111