Intel 8086-2, 8086-1 manual

Page 29

8086

Table 2. Instruction Set Summary (Continued)

Mnemonic and

Description

Instruction Code

JMP e Unconditional Jump:

Direct within Segment

Direct within Segment-Short

Indirect within Segment

Direct Intersegment

Indirect Intersegment

7 6 5 4 3 2 1 0

7 6 5 4 3 2 1 0

7 6 5 4 3 2 1 0

 

 

 

1 1 1 0 1 0 0 1

disp-low

disp-high

 

 

 

1 1 1 0 1 0 1 1

disp

 

 

 

 

1 1 1 1 1 1 1 1

mod 1 0 0 r/m

 

 

 

 

1 1 1 0 1 0 1 0

offset-low

offset-high

 

 

 

 

seg-low

seg-high

 

 

 

1 1 1 1 1 1 1 1

mod 1 0 1 r/m

 

RET e Return from CALL:

 

 

 

Within Segment

1 1 0 0 0 0 1 1

 

 

 

 

 

 

Within Seg Adding Immed to SP

1 1 0 0 0 0 1 0

data-low

data-high

 

 

 

 

Intersegment

1 1 0 0 1 0 1 1

 

 

 

 

 

 

Intersegment Adding Immediate to SP

1 1 0 0 1 0 1 0

data-low

data-high

JE/JZ e Jump on Equal/Zero

 

 

 

0 1 1 1 0 1 0 0

disp

 

JL/JNGE e Jump on Less/Not Greater

 

 

 

0 1 1 1 1 1 0 0

disp

 

or Equal

 

 

 

 

JLE/JNG e Jump on Less or Equal/

 

 

 

0 1 1 1 1 1 1 0

disp

 

Not Greater

 

 

 

 

JB/JNAE e Jump on Below/Not Above

 

 

 

0 1 1 1 0 0 1 0

disp

 

or Equal

 

 

 

 

JBE/JNA e Jump on Below or Equal/

 

 

 

0 1 1 1 0 1 1 0

disp

 

Not Above

 

 

 

 

JP/JPE e Jump on Parity/Parity Even

0 1 1 1 1 0 1 0

disp

 

JO e Jump on Overflow

 

 

 

0 1 1 1 0 0 0 0

disp

 

JS e Jump on Sign

 

 

 

0 1 1 1 1 0 0 0

disp

 

JNE/JNZ e Jump on Not Equal/Not Zero

 

 

 

0 1 1 1 0 1 0 1

disp

 

JNL/JGE e Jump on Not Less/Greater

 

 

 

0 1 1 1 1 1 0 1

disp

 

or Equal

 

 

 

 

JNLE/JG e Jump on Not Less or Equal/

 

 

 

0 1 1 1 1 1 1 1

disp

 

Greater

 

 

 

 

JNB/JAE e Jump on Not Below/Above

 

 

 

0 1 1 1 0 0 1 1

disp

 

or Equal

 

 

 

 

JNBE/JA e Jump on Not Below or

 

 

 

0 1 1 1 0 1 1 1

disp

 

Equal/Above

 

 

 

 

JNP/JPO e Jump on Not Par/Par Odd

0 1 1 1 1 0 1 1

disp

 

JNO e Jump on Not Overflow

 

 

 

0 1 1 1 0 0 0 1

disp

 

JNS e Jump on Not Sign

 

 

 

0 1 1 1 1 0 0 1

disp

 

LOOP e Loop CX Times

1 1 1 0 0 0 1 0

disp

 

LOOPZ/LOOPE e Loop While Zero/Equal

 

 

 

1 1 1 0 0 0 0 1

disp

 

LOOPNZ/LOOPNE e Loop While Not

 

 

 

1 1 1 0 0 0 0 0

disp

 

Zero/Equal

 

 

 

 

JCXZ e Jump on CX Zero

1 1 1 0 0 0 1 1

disp

 

INT e Interrupt

Type Specified

Type 3

INTO e Interrupt on Overflow

IRET e Interrupt Return

1 1 0 0 1 1 0 1

type

1 1 0 0 1 1 0 0

1 1 0 0 1 1 1 0

1 1 0 0 1 1 1 1

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Image 29
Contents CPU Block Diagram Pin ConfigurationBHE LOW BHE/SReady ResetIntr TestHigh LOWRQ/GT0 RQ/GT1ALE IntaDT/R DENFunctional Description BUS Operation Minimum and Maximum ModesMinimum Mode 8086 Typical Configuration Write I/O Read I/OInstruction Fetch Read Data from MemoryAlternate Data extra segment Processor Reset and InitializationAddressing Interrupt OperationsREAD/MODIFY/WRITE Semaphore Operations VIA Lock Maskable Interrupt IntrHalt System TIMING-MINIMUM System External Synchronization VIA TestBUS TIMING-MEDIUM Size Systems Absolute Maximum Ratings Tclcl Minimum Complexity System Timing RequirementsTclch TchclTiming Responses CharacteristicsWaveforms Testing INPUT, Output Waveform Testing Load CircuitMinimum Mode Waveforms Minimum Mode Tinvch CharacteristicsNMI, Test Tgvch TchgxTclmh TclmlTryhsh TchsvTCLCL-45 TCLCL-35 TCLCL-40 TrhavTchdtl TchdthMaximum Mode Waveforms Maximum Mode BUS Lock Signal Timing Maximum Mode Only Reset Timing Asynchronous Signal RecognitionREQUEST/GRANT Sequence Timing Maximum Mode only WaveformsHOLD/HOLD Acknowledge Timing Minimum Mode only Data Transfer Instruction Set SummaryArithmetic Logic 8086 Bit w e Segment 000 001 010 011 100 101 110 111 Data Sheet Revision Review1 reg 1 1