Intel 8086-2, 8086-1 manual Absolute Maximum Ratings

Page 14

8086

ABSOLUTE MAXIMUM RATINGS*

Ambient Temperature Under Bias ÀÀÀÀÀÀ0§C to 70§C Storage Temperature ÀÀÀÀÀÀÀÀÀÀb65§C to a150§C

Voltage on Any Pin with

Respect to GroundÀÀÀÀÀÀÀÀÀÀÀÀÀÀb1.0V to a7V

Power DissipationÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ2.5W

NOTICE: This is a production data sheet. The specifi- cations are subject to change without notice.

*WARNING: Stressing the device beyond the ‘‘Absolute Maximum Ratings’’ may cause permanent damage. These are stress ratings only. Operation beyond the ‘‘Operating Conditions’’ is not recommended and ex- tended exposure beyond the ‘‘Operating Conditions’’ may affect device reliability.

D.C. CHARACTERISTICS (8086: TA e 0§C to 70§C, VCC e 5V g10%)

(8086-1: TA e 0§C to 70§C, VCC e 5V g5%)

(8086-2: TA e 0§C to 70§C, VCC e 5V g5%)

Symbol

Parameter

Min

Max

Units

Test Conditions

 

 

 

 

 

 

 

 

 

 

 

 

VIL

Input Low Voltage

b0.5

a0.8

V

(Note 1)

VIH

Input High Voltage

2.0

VCC a 0.5

V

(Notes 1, 2)

VOL

Output Low Voltage

 

0.45

V

IOL e 2.5 mA

VOH

Output High Voltage

2.4

 

V

IOH e b 400 mA

ICC

Power Supply Current: 8086

 

340

 

TA e 25§C

 

8086-1

 

 

 

 

 

 

 

360

mA

 

8086-2

 

 

 

 

 

 

 

350

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ILI

Input Leakage Current

 

g10

mA

0V s VIN s VCC (Note 3)

ILO

Output Leakage Current

 

g10

mA

0.45V s VOUT s VCC

VCL

Clock Input Low Voltage

b0.5

a0.6

V

 

VCH

Clock Input High Voltage

3.9

VCC a 1.0

V

 

CIN

Capacitance of Input Buffer

 

15

pF

fc e 1 MHz

 

(All input except

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

AD0 – AD15, RQ/GT)

 

 

 

 

CIO

Capacitance of I/O Buffer

 

15

pF

fc e 1 MHz

 

 

 

 

 

 

 

 

 

 

 

(AD0 – AD15, RQ/GT)

 

 

 

 

NOTES:

1.VIL tested with MN/MX Pin e 0V. VIH tested with MN/MX Pin e 5V. MN/MX Pin is a Strap Pin.

2.Not applicable to RQ/GT0 and RQ/GT1 (Pins 30 and 31).

3.HOLD and HLDA ILI min e 30 mA, max e 500 mA.

14

Image 14
Contents Pin Configuration CPU Block DiagramLOW BHE/S BHEIntr ResetReady TestRQ/GT0 LOWHigh RQ/GT1DT/R IntaALE DENFunctional Description Minimum and Maximum Modes BUS OperationMinimum Mode 8086 Typical Configuration Instruction Fetch Read I/OWrite I/O Read Data from MemoryAddressing Processor Reset and InitializationAlternate Data extra segment Interrupt OperationsREAD/MODIFY/WRITE Semaphore Operations VIA Lock Maskable Interrupt IntrHalt External Synchronization VIA Test System TIMING-MINIMUM SystemBUS TIMING-MEDIUM Size Systems Absolute Maximum Ratings Tclch Minimum Complexity System Timing RequirementsTclcl TchclCharacteristics Timing ResponsesWaveforms Testing INPUT, Output Waveform Testing Load CircuitMinimum Mode Waveforms Minimum Mode NMI, Test Tgvch CharacteristicsTinvch TchgxTryhsh TclmlTclmh TchsvTchdtl TrhavTCLCL-45 TCLCL-35 TCLCL-40 TchdthMaximum Mode Waveforms Maximum Mode REQUEST/GRANT Sequence Timing Maximum Mode only Asynchronous Signal RecognitionBUS Lock Signal Timing Maximum Mode Only Reset Timing WaveformsHOLD/HOLD Acknowledge Timing Minimum Mode only Instruction Set Summary Data TransferArithmetic Logic 8086 Bit w e Segment 000 001 010 011 100 101 110 111 Data Sheet Revision Review1 reg 1 1