Intel 8086-1 manual Trhav, TCLCL-45 TCLCL-35 TCLCL-40, Tchdtl, Tchdth, Tclgl, Tclgh, Trlrh, Tohol

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8086

A.C. CHARACTERISTICS (Continued)

TIMING RESPONSES (Continued)

Symbol

Parameter

8086

 

8086-1

 

8086-2

 

Units

Test

 

 

 

 

 

 

 

 

Min

Max

Min

Max

Min

Max

 

Conditions

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TRHAV

RD Inactive to Next

TCLCL-45

 

TCLCL-35

 

TCLCL-40

 

ns

 

 

Address Active

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CL e 20 – 100 pF

TCHDTL

Direction Control

 

50

 

50

 

50

ns

 

Active Delay

 

 

 

 

 

 

 

for all 8086

 

(Note 1)

 

 

 

 

 

 

 

Outputs (In

 

 

 

 

 

 

 

 

addition to 8086

 

 

 

 

 

 

 

 

 

TCHDTH

Direction Control

 

30

 

30

 

30

ns

 

 

 

self-load)

 

 

 

 

 

 

 

 

 

 

Inactive Delay

 

 

 

 

 

 

 

 

 

(Note 1)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TCLGL

GT Active Delay

0

85

0

38

0

50

ns

 

 

 

 

 

 

 

 

 

 

 

TCLGH

GT Inactive Delay

0

85

0

45

0

50

ns

 

 

 

 

 

 

 

 

 

 

 

TRLRH

RD Width

2TCLCL-75

 

2TCLCL-40

 

2TCLCL-50

 

ns

 

 

 

 

 

 

 

 

 

 

 

TOLOH

Output Rise Time

 

20

 

20

 

20

ns

From 0.8V to 2.0V

 

 

 

 

 

 

 

 

 

 

TOHOL

Output Fall Time

 

12

 

12

 

12

ns

From 2.0V to 0.8V

 

 

 

 

 

 

 

 

 

 

NOTES:

1.Signal at 8284A or 8288 shown for reference only.

2.Setup requirement for asynchronous signal only to guarantee recognition at next CLK.

3.Applies only to T3 and wait states.

4.Applies only to T2 state (8 ns into T3).

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Image 21
Contents CPU Block Diagram Pin ConfigurationBHE LOW BHE/SReady ResetIntr TestHigh LOWRQ/GT0 RQ/GT1ALE IntaDT/R DENFunctional Description BUS Operation Minimum and Maximum ModesMinimum Mode 8086 Typical Configuration Write I/O Read I/OInstruction Fetch Read Data from MemoryAlternate Data extra segment Processor Reset and InitializationAddressing Interrupt OperationsMaskable Interrupt Intr HaltREAD/MODIFY/WRITE Semaphore Operations VIA Lock System TIMING-MINIMUM System External Synchronization VIA TestBUS TIMING-MEDIUM Size Systems Absolute Maximum Ratings Tclcl Minimum Complexity System Timing RequirementsTclch TchclTiming Responses CharacteristicsTesting INPUT, Output Waveform Testing Load Circuit Minimum ModeWaveforms Waveforms Minimum Mode Tinvch CharacteristicsNMI, Test Tgvch TchgxTclmh TclmlTryhsh TchsvTCLCL-45 TCLCL-35 TCLCL-40 TrhavTchdtl TchdthMaximum Mode Waveforms Maximum Mode BUS Lock Signal Timing Maximum Mode Only Reset Timing Asynchronous Signal RecognitionREQUEST/GRANT Sequence Timing Maximum Mode only WaveformsHOLD/HOLD Acknowledge Timing Minimum Mode only Data Transfer Instruction Set SummaryArithmetic Logic 8086 Data Sheet Revision Review 1 reg 1 1Bit w e Segment 000 001 010 011 100 101 110 111