Intel 8086-1 Minimum Complexity System Timing Requirements, Tclcl, Tclch, Tchcl, TCH1CH2, TCL2CL1

8086

A.C. CHARACTERISTICS (8086: TA e 0§C to 70§C, VCC e 5V g 10%)

(8086-1: TA e 0§C to 70§C, VCC e 5V g 5%)

(8086-2: TA e 0§C to 70§C, VCC e 5V g 5%)

MINIMUM COMPLEXITY SYSTEM TIMING REQUIREMENTS

Symbol	Parameter	8086		8086-1		8086-2		Units	Test Conditions
		Min	Max	Min	Max	Min	Max
TCLCL	CLK Cycle Period	200	500	100	500	125	500	ns
TCLCH	CLK Low Time	118		53		68		ns
TCHCL	CLK High Time	69		39		44		ns
TCH1CH2	CLK Rise Time		10		10		10	ns	From 1.0V to 3.5V
TCL2CL1	CLK Fall Time		10		10		10	ns	From 3.5V to 1.0V
TDVCL	Data in Setup Time	30		5		20		ns
TCLDX	Data in Hold Time	10		10		10		ns
TR1VCL	RDY Setup Time	35		35		35		ns
	into 8284A (See
	Notes 1, 2)
TCLR1X	RDY Hold Time	0		0		0		ns
	into 8284A (See
	Notes 1, 2)
TRYHCH	READY Setup	118		53		68		ns
	Time into 8086
TCHRYX	READY Hold Time	30		20		20		ns
	into 8086
TRYLCL	READY Inactive to	b8		b10		b8		ns
	CLK (See Note 3)
THVCH	HOLD Setup Time	35		20		20		ns
TINVCH	INTR, NMI, TEST	30		15		15		ns
	Setup Time (See
	Note 2)
TILIH	Input Rise Time		20		20		20	ns	From 0.8V to 2.0V
	(Except CLK)
TIHIL	Input Fall Time		12		12		12	ns	From 2.0V to 0.8V
	(Except CLK)

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