Intel E8500 manual Reference Documents, Xmb

Introduction

XMB	Intel® E8500 chipset eXternal Memory Bridge Component. The chipset
	component that bridges the IMI and DDR interfaces.

1.3Reference Documents

The reader of this specification should also be familiar with material and concepts presented in the following documents:

•Intel® 82801EB I/O Controller Hub 5 (ICH5) and Intel® 82801ER I/O Controller Hub 5 R (ICH5R) Thermal Design Guide

•Intel® 82801EB I/O Controller Hub 5 (ICH5) and Intel® 82801ER I/O Controller Hub 5 R (ICH5R) Datasheet

•Intel® 6700PXH 64-bit PCI Hub Thermal/Mechanical Design Guidelines

•Intel® 6700PXH 64-bit PCI Hub Datasheet

•Intel® E8500 Chipset North Bridge (NB) Datasheet

•Intel® E8500 Chipset North Bridge (NB) Specification Update

•Intel® E8500 Chipset eXternal Memory Bridge (XMB) Datasheet

•Intel® E8500 Chipset eXternal Memory Bridge (XMB) Specification Update

•64-bit Intel® Xeon™ Processor MP with up to 8MB L3 Cache Datasheet

•64-bit Intel® Xeon™ Processor MP with up to 8MB L3 Cache Thermal/Mechanical Design Guidelines

•64-bit Intel® Xeon™ Processor MP with 1MB L2 Cache Datasheet

•64-bit Intel® Xeon™ Processor MP with 1MB L2 Cache Thermal/Mechanical Design Guidelines

•BGA/OLGA Assembly Development Guide

•Various system thermal design suggestions (http://www.formfactors.org)

Note: Unless otherwise specified, these documents are available through your Intel field sales representative. Some documents may not be available at this time.

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Intel® E8500 Chipset North Bridge (NB) and eXternal Memory	9
Bridge (XMB) Thermal/Mechanical Design Guide