Intel 6300ESB ICH Platform Management, Power Button, Soft Off, Sleep States Supported, 1 S0 State

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Platform Management

Platform Management

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The following sections describe how the system power management operates and how the different ACPI states are implemented. Platform management involves:

ACPI implementation specific details

System monitoring, control and response to thermal, voltage and intrusion events

BIOS security

2.1Power Button

The system power button is connected to the I/O controller component. When the button is pressed, the I/O controller receives the signal and transitions the system to the proper sleep state as determined by the operating system and software. If the power button is pressed and held for four seconds, the system powers off (S5 state). This feature is called power button override and is particularly helpful in case of system hang and system lock.

2.2Soft Off

The I/O controller incorporates a SLP_S4 output signal which routes to the power supply. This signal has register access that allows software to deactivate the power supply. When SLP_S4 goes active, the power supply cuts main power but keeps 5 V auxiliary power rails available. 5 V auxiliary voltage is active while the power supply receives AC power.

2.3Sleep States Supported

The I/O controller controls the system sleep states. States S0, S1, S3, S4, and S5 are supported. The platform enters sleep states in response to BIOS, operating system or user actions. Normally the operating system determines which sleep state to transition into. However, a four-second power button override event places the system immediately into S5. When transitioning into a software- invoked sleep state, the I/O controller attempts to gracefully put the system to sleep by first going into the processor C2 state.

2.3.1S0 State

This is the normal operating state, even though there are some power savings modes in this state using processor Halt and Stop Clock (processor C1 and C2 states). S0 affords the fastest wake-up response time of any sleep state because the system remains fully powered and memory is intact.

Intel® Xeon™ Processor, Intel® E7520 Chipset, Intel® 6300ESB ICH Development Kit User’s Manual

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Contents September User’s ManualContents Contents Contents Tables FiguresDate Revision Description Revision HistoryProduct Overview Product ContentsRelated Documents Products Feature List Block Diagram +$&0,,+ Dimm Placement DDR2 Dimm Placement DDR2Memory Subsystem Supported Dimm Module TypesDDR2 400 Memory Dimm Ordering Memory Population Rules and ConfigurationsPlatform Management Power ButtonSoft Off Sleep States Supported3 S2 State 2 S1 State4 S3 State 5 S4 StatePlatform Management PCI PM SupportProcessor Thermal Management System Fan OperationEquipment Required for CRB Usage PrecautionsDrivers included on CD Driver and OS RequirementsEquipment Required for CRB Usage Windows Compatible Driver Package Contents Jumpers Jumpers and HeadersRef Des Description/Settings Jumper Settings Sheet 1BSEL0 J4J3 Jumper Settings Sheet 2Ichsmbclk Jumper Settings Sheet 3Block Diagram Power DiagramsSystem Overview Platform Clocking Clock Block DiagramPlatform Reset Diagram Platform ResetsSMBus SMBus Block DiagramPlatform IRQ Routing IRQ Routing DiagramVRD VID Headers Processor VRD Settings Sheet 1Processor VRD Settings Sheet 2 Miscellaneous Buttons Power ButtonsLevel 1 Debug Port 80/BIOS Debug ProcedureLevel 1 Debug Port 80/BIOS Test Pass/Fail Criteria Cause of FailureLevel 2 Debug Power Sequence Level 2 Debug Power SequenceLevel 3 Debug Voltage References Level 3 Debug Voltage ReferencesComponents Requiring Heat Sink Assembly Heatsink AssemblyComponent Quantity per BoardInserting Processor in Socket Processor Heat Sink Installation InstructionsInstalling the Processor Backplate Installing the Heatsink