Intel Xeon, 6300ESB ICH user manual VRD VID Headers, Processor VRD Settings Sheet 1

Page 30

System Overview

5.6VRD VID Headers

Provides for manual control of the processor core voltage regulator output level(s). Normally, the processor should be run at its default VID (voltage identification) value as set during manufacturing. However, in the event the user needs to set a different VID value from the default value, it can be accomplished through a jumper block found on the board. Note that these headers are not populated by default.

The CPU 0 VID header is located at J9K2. CPU 1 VID header is located at J4K1. Table 5 provides the VID settings available via the VID headers.

Table 5.

Processor VRD Settings (Sheet 1 of 2)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VID5

VID4

VID3

VID2

VID1

VID0

VCC_MAX

 

VID5

VID4

VID3

VID2

VID1

VID0

VCC_MAX

(V)

 

(V)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

0

1

0

1

0

0.8375

 

0

1

1

0

1

0

1.2125

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

0

1

0

0

1

0.8500

 

1

1

1

0

0

1

1.2250

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

0

1

0

0

1

0.8625

 

0

1

1

0

0

1

1.2375

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

0

1

0

0

0

0.8750

 

1

1

1

0

0

0

1.2500

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

0

1

0

0

0

0.8875

 

0

1

1

0

0

0

1.2625

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

0

0

1

1

1

0.9000

 

1

1

0

1

1

1

1.2750

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

0

0

1

1

1

0.9125

 

0

1

0

1

1

1

1.2875

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

0

0

1

1

0

0.9250

 

1

1

0

1

1

0

1.3000

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

0

0

1

1

0

0.9375

 

0

1

0

1

1

0

1.3125

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

0

0

1

0

1

0.9500

 

1

1

0

1

0

1

1.3250

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

0

0

1

0

1

0.9625

 

0

1

0

1

0

1

1.3375

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

0

0

1

0

0

0.9750

 

1

1

0

1

0

0

1.3500

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

0

0

1

0

0

0.9875

 

0

1

0

1

0

0

1.3625

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

0

0

0

1

1

1.0000

 

1

1

0

0

1

1

1.3750

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

0

0

0

1

1

1.0125

 

0

1

0

0

1

1

1.3875

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

0

0

0

1

0

1.0250

 

1

1

0

0

1

0

1.400

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

0

0

0

1

0

1.0375

 

0

1

0

0

1

0

1.4125

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

0

0

0

0

1

1.0500

 

1

1

0

0

0

1

1.4250

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

0

0

0

0

1

1.0625

 

0

1

0

0

0

1

1.4375

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

0

0

0

0

0

1.0750

 

1

1

0

0

0

0

1.4500

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

0

0

0

0

0

1.0875

 

0

1

0

0

0

0

1.4625

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

1

1

1

1

1

OFF

 

1

0

1

1

1

1

1.4750

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

30Intel® Xeon™ Processor, Intel® E7520 Chipset, Intel® 6300ESB ICH Development Kit User’s Manual

Image 30
Contents User’s Manual SeptemberContents Contents Contents Figures TablesRevision History Date Revision DescriptionProduct Contents Product OverviewRelated Documents Products Feature List Block Diagram +$&0,,+ Memory Subsystem Dimm Placement DDR2Dimm Placement DDR2 Supported Dimm Module TypesMemory Population Rules and Configurations DDR2 400 Memory Dimm OrderingSoft Off Power ButtonPlatform Management Sleep States Supported4 S3 State 2 S1 State3 S2 State 5 S4 StatePCI PM Support Platform ManagementSystem Fan Operation Processor Thermal ManagementPrecautions Equipment Required for CRB UsageDriver and OS Requirements Drivers included on CDEquipment Required for CRB Usage Windows Compatible Driver Package Contents Jumpers and Headers JumpersJumper Settings Sheet 1 Ref Des Description/SettingsJumper Settings Sheet 2 BSEL0 J4J3Jumper Settings Sheet 3 IchsmbclkPower Diagrams Block DiagramSystem Overview Clock Block Diagram Platform ClockingPlatform Resets Platform Reset DiagramSMBus Block Diagram SMBusIRQ Routing Diagram Platform IRQ RoutingProcessor VRD Settings Sheet 1 VRD VID HeadersProcessor VRD Settings Sheet 2 Power Buttons Miscellaneous ButtonsLevel 1 Debug Port 80/BIOS Debug ProcedureLevel 1 Debug Port 80/BIOS Test Pass/Fail Criteria Cause of FailureLevel 3 Debug Voltage References Level 2 Debug Power SequenceLevel 2 Debug Power Sequence Level 3 Debug Voltage ReferencesComponent Quantity per Heatsink AssemblyComponents Requiring Heat Sink Assembly BoardProcessor Heat Sink Installation Instructions Inserting Processor in SocketInstalling the Processor Backplate Installing the Heatsink