Intel 6300ESB ICH, Xeon user manual Debug Procedure, Level 1 Debug Port 80/BIOS

Page 33

 

Debug Procedure

Debug Procedure

6

 

 

 

 

The debug procedures in this section are used to determine baseline functionality for the Intel® Xeon™ Processor with 800 MHz System Bus, Intel® E7520 Chipset, and Intel® 6300ESB ICH Development Kit. This is a cursory set of tests designed to provide a level of confidence in the platform operation.

6.1Level 1 Debug (Port 80/BIOS)

Refer to the steps in Table 6 when debugging a board that does not boot.

Table 6.

Level 1 Debug (Port 80/BIOS)

 

 

 

 

 

 

Item

 

Test

Pass/Fail Criteria

Cause of Failure

 

 

 

 

 

1

Verify “SYSTEM PWRGD” LED

CR2H1: Green

Power Sequence Failure—go immediately to Level 2

debug

 

 

 

 

 

 

 

 

2

Is “PCI Reset” LED (decimal on

Decimal on Port 80 display

PCI Reset Stuck—go to Level 3 debug

DS1J2) illuminated?

Red

 

 

 

 

 

 

3

Verify CPURST LED is off

CR7K3: Off

CPU Reset Stuck—go to Level 3 debug

 

 

 

 

 

 

 

 

Port 80 LEDs are posting

System Hang—Check BIOS go to level 3 debug. Refer

4

Verify Port 80 Posting

to AMI* BIOS documentation for details. Also refer to

boot codes and stopping

 

 

 

Schematic Page 68, Coord. D5.

 

 

 

 

 

 

 

 

 

5

Check BIOS revision

Latest BIOS installed

Contact your Intel Representative for the latest BIOS

image.

 

 

 

 

 

 

 

 

6

Verify default Jumper settings

See default settings

Improper Jumper settings

 

 

 

 

 

Intel® Xeon™ Processor, Intel® E7520 Chipset, Intel® 6300ESB ICH Development Kit User’s Manual

33

Image 33
Contents September User’s ManualContents Contents Contents Tables FiguresDate Revision Description Revision HistoryProduct Contents Product OverviewRelated Documents Products Feature List Block Diagram +$&0,,+ Dimm Placement DDR2 Dimm Placement DDR2Memory Subsystem Supported Dimm Module TypesDDR2 400 Memory Dimm Ordering Memory Population Rules and ConfigurationsPlatform Management Power ButtonSoft Off Sleep States Supported3 S2 State 2 S1 State4 S3 State 5 S4 StatePlatform Management PCI PM SupportProcessor Thermal Management System Fan OperationEquipment Required for CRB Usage PrecautionsDrivers included on CD Driver and OS RequirementsEquipment Required for CRB Usage Windows Compatible Driver Package Contents Jumpers Jumpers and HeadersRef Des Description/Settings Jumper Settings Sheet 1BSEL0 J4J3 Jumper Settings Sheet 2Ichsmbclk Jumper Settings Sheet 3Power Diagrams Block DiagramSystem Overview Platform Clocking Clock Block DiagramPlatform Reset Diagram Platform ResetsSMBus SMBus Block DiagramPlatform IRQ Routing IRQ Routing DiagramVRD VID Headers Processor VRD Settings Sheet 1Processor VRD Settings Sheet 2 Miscellaneous Buttons Power ButtonsLevel 1 Debug Port 80/BIOS Debug ProcedureLevel 1 Debug Port 80/BIOS Test Pass/Fail Criteria Cause of FailureLevel 2 Debug Power Sequence Level 2 Debug Power SequenceLevel 3 Debug Voltage References Level 3 Debug Voltage ReferencesComponents Requiring Heat Sink Assembly Heatsink AssemblyComponent Quantity per BoardInserting Processor in Socket Processor Heat Sink Installation InstructionsInstalling the Processor Backplate Installing the Heatsink