Cypress CY7C1515JV18 manual TAP AC Switching Characteristics, TAP Timing and Test Conditions

Page 17
TAP AC Switching Characteristics

CY7C1511JV18, CY7C1526JV18

CY7C1513JV18, CY7C1515JV18

TAP AC Switching Characteristics

Over the Operating Range [15, 16]

Parameter

Description

Min

Max

Unit

tTCYC

TCK Clock Cycle Time

50

 

ns

tTF

TCK Clock Frequency

 

20

MHz

tTH

TCK Clock HIGH

20

 

ns

tTL

TCK Clock LOW

20

 

ns

Setup Times

 

 

 

 

 

 

 

 

 

tTMSS

TMS Setup to TCK Clock Rise

5

 

ns

tTDIS

TDI Setup to TCK Clock Rise

5

 

ns

tCS

Capture Setup to TCK Rise

5

 

ns

Hold Times

 

 

 

 

tTMSH

TMS Hold after TCK Clock Rise

5

 

ns

tTDIH

TDI Hold after Clock Rise

5

 

ns

tCH

Capture Hold after Clock Rise

5

 

ns

Output Times

 

 

 

 

 

 

 

 

 

tTDOV

TCK Clock LOW to TDO Valid

 

10

ns

tTDOX

TCK Clock LOW to TDO Invalid

0

 

ns

TAP Timing and Test Conditions

Figure 2 shows the TAP timing and test conditions. [16]

Figure 2. TAP Timing and Test Conditions

 

 

 

0.9V

 

 

 

 

 

 

50Ω

 

 

 

 

 

 

 

 

 

 

 

 

TDO

 

 

 

 

 

 

Z0

= 50Ω

 

 

 

CL = 20 pF

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ALL INPUT PULSES

1.8V

0.9V

0V

(a)GND

Test Clock

TCK

Test Mode Select

TMS

Test Data In

TDI

Test Data Out

TDO

tTH

tTMSS

tTDIS

tTL

tTCYC

tTMSH TAP Timing and Test Conditions

tTDIH Manual backgroundManual background

tTDOV

 

 

 

t

 

 

 

 

 

 

 

 

TDOX

Notes

15.tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register.

16.Test conditions are specified using the load in TAP AC Test Conditions. tR/tF = 1 ns.

Document Number: 001-12560 Rev. *C

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Contents Configurations FeaturesCY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 Functional DescriptionCY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 Logic Block Diagram CY7C1511JV18Logic Block Diagram CY7C1526JV18 Logic Block Diagram CY7C1515JV18 Logic Block Diagram CY7C1513JV18165-Ball FBGA 15 x 17 x 1.4 mm Pinout Pin Configuration165-Ball FBGA 15 x 17 x 1.4 mm Pinout Pin Definitions CY7C1511JV18, CY7C1526JV18CY7C1513JV18, CY7C1515JV18 Pin Definitions continued CY7C1513JV18, CY7C1515JV18Read Operations Functional OverviewWrite Operations Byte Write OperationsDepth Expansion Concurrent TransactionsProgrammable Impedance Echo ClocksApplication Example CY7C1511JV18, CY7C1526JV18Truth Table ASICWrite Cycle Descriptions Write Cycle Descriptions Test Access Port-Test Clock Disabling the JTAG FeaturePerforming a TAP Reset IEEE 1149.1 Serial Boundary Scan JTAGSAMPLE Z IDCODESAMPLE/PRELOAD BYPASSPage 15 of TAP Controller State DiagramTAP Electrical Characteristics TAP Controller Block DiagramTAP Timing and Test Conditions TAP AC Switching CharacteristicsScan Register Sizes Identification Register DefinitionsInstruction Codes CY7C1511JV18Boundary Scan Order Power Up Waveforms Power Up Sequence in QDR-II SRAMPower Up Sequence DLL ConstraintsDC Electrical Characteristics Electrical CharacteristicsAC Electrical Characteristics Maximum RatingsThermal Resistance CapacitanceAC Test Loads and Waveforms PackageParameter Switching CharacteristicsREAD Switching WaveformsWRITE K K RPS WPSOrdering Information Figure 4. 165-ball FBGA 15 x 17 x 1.40 mm Package DiagramISSUE Document History PageBurst Architecture Document Number ECN NO