Cypress manual CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18, + Feedback

CY7C1511JV18, CY7C1526JV18

CY7C1513JV18, CY7C1515JV18

Logic Block Diagram (CY7C1511JV18)

8

D[7:0]

21Address

A(20:0) Register

K

K CLK

Gen.

DOFF

VREF
		Control
WPS
		Logic
NWS
	[1:0]

	Write	Write	Write	Write
	Reg	Reg	Reg	Reg
Decode	2M x	2M x	2M x	2M x	Decode
Write Add.	8 Array	8 Array	8 Array	8 Array	Read Add.
	Read Data Reg.
		32	16			Reg.
			16
							Reg.

Address					21		A(20:0)
Register
	Control					RPS
		Logic				C
						C
									CQ
								CQ
				8
			Reg.
				8		8
				8				Q[7:0]
				8

Logic Block Diagram (CY7C1526JV18)

9

D[8:0]

21Address

A(20:0) Register

K

K CLK

Gen.

DOFF

VREF
		Control
WPS
		Logic
BWS
	[0]

	Write	Write	Write	Write
	Reg	Reg	Reg	Reg
Decode	2M x	2M x	2M x	2M x	Decode
Write Add.	9 Array	9 Array	9 Array	9 Array	Read Add.
	Read Data Reg.
		36	18			Reg.
			18
							Reg.

Address					21		A(20:0)
Register
	Control					RPS
		Logic				C
						C
									CQ
								CQ
				9
			Reg.
				9		9
				9				Q[8:0]
				9

Document Number: 001-12560 Rev. *C Page 2 of 27

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