Cypress manual Ordering Information, CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18

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Ordering Information

CY7C1511JV18, CY7C1526JV18

CY7C1513JV18, CY7C1515JV18

Ordering Information

Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered.

Speed	Ordering Code	Package	Package Type	Operating
(MHz)	Ordering Code	Diagram	Package Type	Range
300	CY7C1511JV18-300BZC	51-85195	165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)	Commercial

	CY7C1526JV18-300BZC

	CY7C1513JV18-300BZC

	CY7C1515JV18-300BZC

	CY7C1511JV18-300BZXC	51-85195	165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free

	CY7C1526JV18-300BZXC

	CY7C1513JV18-300BZXC

	CY7C1515JV18-300BZXC

	CY7C1511JV18-300BZI	51-85195	165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)	Industrial

	CY7C1526JV18-300BZI

	CY7C1513JV18-300BZI

	CY7C1515JV18-300BZI

	CY7C1511JV18-300BZXI	51-85195	165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free

	CY7C1526JV18-300BZXI

	CY7C1513JV18-300BZXI

	CY7C1515JV18-300BZXI

Document Number: 001-12560 Rev. *C

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Contents Configurations FeaturesCY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 Functional DescriptionLogic Block Diagram CY7C1526JV18 Logic Block Diagram CY7C1511JV18CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 Logic Block Diagram CY7C1515JV18 Logic Block Diagram CY7C1513JV18165-Ball FBGA 15 x 17 x 1.4 mm Pinout Pin ConfigurationCY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 CY7C1513JV18, CY7C1515JV18 CY7C1511JV18, CY7C1526JV18Pin Definitions Pin Definitions continued CY7C1513JV18, CY7C1515JV18Read Operations Functional OverviewWrite Operations Byte Write OperationsDepth Expansion Concurrent TransactionsProgrammable Impedance Echo ClocksApplication Example CY7C1511JV18, CY7C1526JV18Truth Table ASICWrite Cycle Descriptions Write Cycle Descriptions Test Access Port-Test Clock Disabling the JTAG FeaturePerforming a TAP Reset IEEE 1149.1 Serial Boundary Scan JTAGSAMPLE Z IDCODESAMPLE/PRELOAD BYPASSPage 15 of TAP Controller State DiagramTAP Electrical Characteristics TAP Controller Block DiagramTAP Timing and Test Conditions TAP AC Switching CharacteristicsScan Register Sizes Identification Register DefinitionsInstruction Codes CY7C1511JV18Boundary Scan Order Power Up Waveforms Power Up Sequence in QDR-II SRAMPower Up Sequence DLL ConstraintsDC Electrical Characteristics Electrical CharacteristicsAC Electrical Characteristics Maximum RatingsThermal Resistance CapacitanceAC Test Loads and Waveforms PackageParameter Switching CharacteristicsREAD Switching WaveformsWRITE K K RPS WPSOrdering Information Figure 4. 165-ball FBGA 15 x 17 x 1.40 mm Package DiagramISSUE Document History PageBurst Architecture Document Number ECN NO