Cypress CY7C1513JV18 Power Up Sequence in QDR-II SRAM, Power Up Waveforms, DLL Constraints, ~ ~

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Power Up Sequence in QDR-II SRAM

CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18

Power Up Sequence in QDR-II SRAM

QDR-II SRAMs must be powered up and initialized in a predefined manner to prevent undefined operations. During Power Up, when the DOFF is tied HIGH, the DLL gets locked after 1024 cycles of stable clock.

Power Up Sequence

■Apply power and drive DOFF HIGH (All other inputs can be HIGH or LOW).

❐Apply VDD before VDDQ.

❐Apply VDDQ before VREF or at the same time as VREF.

■Provide stable power and clock (K, K) for 1024 cycles to lock the DLL.

Power Up Waveforms

DLL Constraints

■DLL uses K clock as its synchronizing input. The input must have low phase jitter, which is specified as tKC Var.

■The DLL functions at frequencies down to 120 MHz.

■If the input clock is unstable and the DLL is enabled, then the DLL may lock onto an incorrect frequency, causing unstable SRAM behavior. To avoid this, provide 1024 cycles stable clock to relock to the desired clock frequency.

~ ~

K

K

 

~ ~

 

Unstable Clock
> 1024 Stable clock
Start Normal

 

 

Operation
Clock Start (Clock Starts after VDD/ V DDQ Stable)
VDD/ VDDQ Power Up SequencePower Up Waveforms VDD/ V DDQ Stable (< +/- 0.1V DC per 50ns )
Fix High (or tied to VDDQ)

DOFF

Document Number: 001-12560 Rev. *C

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Contents Features ConfigurationsCY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 Functional DescriptionCY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 Logic Block Diagram CY7C1511JV18Logic Block Diagram CY7C1526JV18 Logic Block Diagram CY7C1513JV18 Logic Block Diagram CY7C1515JV18Pin Configuration 165-Ball FBGA 15 x 17 x 1.4 mm Pinout165-Ball FBGA 15 x 17 x 1.4 mm Pinout Pin Definitions CY7C1511JV18, CY7C1526JV18CY7C1513JV18, CY7C1515JV18 CY7C1513JV18, CY7C1515JV18 Pin Definitions continuedFunctional Overview Read OperationsWrite Operations Byte Write OperationsConcurrent Transactions Depth ExpansionProgrammable Impedance Echo ClocksCY7C1511JV18, CY7C1526JV18 Application ExampleTruth Table ASICWrite Cycle Descriptions CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 Disabling the JTAG Feature Test Access Port-Test ClockPerforming a TAP Reset IEEE 1149.1 Serial Boundary Scan JTAGIDCODE SAMPLE ZSAMPLE/PRELOAD BYPASSTAP Controller State Diagram Page 15 ofTAP Controller Block Diagram TAP Electrical CharacteristicsTAP AC Switching Characteristics TAP Timing and Test ConditionsIdentification Register Definitions Scan Register SizesInstruction Codes CY7C1511JV18Boundary Scan Order Power Up Sequence in QDR-II SRAM Power Up WaveformsPower Up Sequence DLL ConstraintsElectrical Characteristics DC Electrical CharacteristicsAC Electrical Characteristics Maximum RatingsCapacitance Thermal ResistanceAC Test Loads and Waveforms PackageSwitching Characteristics ParameterSwitching Waveforms READWRITE K K RPS WPSOrdering Information Package Diagram Figure 4. 165-ball FBGA 15 x 17 x 1.40 mmDocument History Page ISSUEBurst Architecture Document Number ECN NO
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