Cypress CY7C1513JV18, CY7C1515JV18 manual Pin Configuration, Ball FBGA 15 x 17 x 1.4 mm Pinout

Page 4

Pin Configuration

CY7C1511JV18, CY7C1526JV18

CY7C1513JV18, CY7C1515JV18

Pin Configuration

The pin configuration for CY7C1511JV18, CY7C1513JV18, and CY7C1515JV18 follow. [1]

165-Ball FBGA (15 x 17 x 1.4 mm) Pinout

CY7C1511JV18 (8M x 8)

1

2

3

4

5

6

7

8

9

10

11

A

A

A

1

NC/144M

A

A

CQ

CQ

WPS

NWS

K

RPS

B

NC

NC

NC

A

NC/288M

K

0

A

NC

NC

Q3

NWS

C

NC

NC

NC

VSS

A

NC

A

VSS

NC

NC

D3

D

NC

D4

NC

VSS

VSS

VSS

VSS

VSS

NC

NC

NC

E

NC

NC

Q4

VDDQ

VSS

VSS

VSS

VDDQ

NC

D2

Q2

F

NC

NC

NC

VDDQ

VDD

VSS

VDD

VDDQ

NC

NC

NC

G

NC

D5

Q5

VDDQ

VDD

VSS

VDD

VDDQ

NC

NC

NC

H

VREF

VDDQ

VDDQ

VDD

VSS

VDD

VDDQ

VDDQ

VREF

ZQ

DOFF

J

NC

NC

NC

VDDQ

VDD

VSS

VDD

VDDQ

NC

Q1

D1

K

NC

NC

NC

VDDQ

VDD

VSS

VDD

VDDQ

NC

NC

NC

L

NC

Q6

D6

VDDQ

VSS

VSS

VSS

VDDQ

NC

NC

Q0

M

NC

NC

NC

VSS

VSS

VSS

VSS

VSS

NC

NC

D0

N

NC

D7

NC

VSS

A

A

A

VSS

NC

NC

NC

P

NC

NC

Q7

A

A

C

A

A

NC

NC

NC

R

TDO

TCK

A

A

A

A

A

A

TMS

TDI

C

CY7C1526JV18 (8M x 9)

1

2

3

4

5

6

7

8

9

10

11

A

A

A

NC

NC/144M

A

A

CQ

CQ

WPS

K

RPS

B

NC

NC

NC

A

NC/288M

K

0

A

NC

NC

Q4

BWS

C

NC

NC

NC

VSS

A

NC

A

VSS

NC

NC

D4

D

NC

D5

NC

VSS

VSS

VSS

VSS

VSS

NC

NC

NC

E

NC

NC

Q5

VDDQ

VSS

VSS

VSS

VDDQ

NC

D3

Q3

F

NC

NC

NC

VDDQ

VDD

VSS

VDD

VDDQ

NC

NC

NC

G

NC

D6

Q6

VDDQ

VDD

VSS

VDD

VDDQ

NC

NC

NC

H

VREF

VDDQ

VDDQ

VDD

VSS

VDD

VDDQ

VDDQ

VREF

ZQ

DOFF

J

NC

NC

NC

VDDQ

VDD

VSS

VDD

VDDQ

NC

Q2

D2

K

NC

NC

NC

VDDQ

VDD

VSS

VDD

VDDQ

NC

NC

NC

L

NC

Q7

D7

VDDQ

VSS

VSS

VSS

VDDQ

NC

NC

Q1

M

NC

NC

NC

VSS

VSS

VSS

VSS

VSS

NC

NC

D1

N

NC

D8

NC

VSS

A

A

A

VSS

NC

NC

NC

P

NC

NC

Q8

A

A

C

A

A

NC

D0

Q0

R

TDO

TCK

A

A

A

A

A

A

TMS

TDI

C

Note

1. NC/144M and NC/288M are not connected to the die and can be tied to any voltage level.

Document Number: 001-12560 Rev. *C

Page 4 of 27

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Contents Features ConfigurationsCY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 Functional DescriptionLogic Block Diagram CY7C1526JV18 Logic Block Diagram CY7C1511JV18CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 Logic Block Diagram CY7C1513JV18 Logic Block Diagram CY7C1515JV18Pin Configuration 165-Ball FBGA 15 x 17 x 1.4 mm PinoutCY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 CY7C1513JV18, CY7C1515JV18 CY7C1511JV18, CY7C1526JV18Pin Definitions CY7C1513JV18, CY7C1515JV18 Pin Definitions continuedFunctional Overview Read OperationsWrite Operations Byte Write OperationsConcurrent Transactions Depth ExpansionProgrammable Impedance Echo ClocksCY7C1511JV18, CY7C1526JV18 Application ExampleTruth Table ASICWrite Cycle Descriptions CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 Disabling the JTAG Feature Test Access Port-Test ClockPerforming a TAP Reset IEEE 1149.1 Serial Boundary Scan JTAGIDCODE SAMPLE ZSAMPLE/PRELOAD BYPASSTAP Controller State Diagram Page 15 ofTAP Controller Block Diagram TAP Electrical CharacteristicsTAP AC Switching Characteristics TAP Timing and Test ConditionsIdentification Register Definitions Scan Register SizesInstruction Codes CY7C1511JV18Boundary Scan Order Power Up Sequence in QDR-II SRAM Power Up WaveformsPower Up Sequence DLL ConstraintsElectrical Characteristics DC Electrical CharacteristicsAC Electrical Characteristics Maximum RatingsCapacitance Thermal ResistanceAC Test Loads and Waveforms PackageSwitching Characteristics ParameterSwitching Waveforms READWRITE K K RPS WPSOrdering Information Package Diagram Figure 4. 165-ball FBGA 15 x 17 x 1.40 mmDocument History Page ISSUEBurst Architecture Document Number ECN NO