Cypress CY7C1515JV18 manual Maximum Ratings, DC Electrical Characteristics, Operating Range

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Maximum Ratings

CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18

Maximum Ratings

Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested.

Storage Temperature

–65°C to +150°C

Ambient Temperature with Power Applied

.... –10°C to +85°C

Supply Voltage on VDD Relative to GND

–0.5V to +2.9V

Supply Voltage on VDDQ Relative to GND

.......–0.5V to +VDD

DC Applied to Outputs in High-Z

–0.5V to VDDQ + 0.3V

DC Input Voltage [13]

–0.5V to V + 0.3V

 

 

DD

Current into Outputs (LOW)

 

20 mA

Static Discharge Voltage (MIL-STD-883, M. 3015)..

> 2001V

Latch-up Current

...................................................

 

> 200 mA

Operating Range

 

 

 

 

 

 

 

 

 

Ambient

VDD [17]

VDDQ [17]

Range

 

Temperature (TA)

Commercial

 

0°C to +70°C

1.8 ± 0.1V

1.4V to

 

 

 

 

VDD

Industrial

 

–40°C to +85°C

 

Electrical Characteristics

DC Electrical Characteristics

Over the Operating Range [14]

Parameter

Description

Test Conditions

 

Min

Typ

Max

Unit

VDD

Power Supply Voltage

 

 

 

1.7

1.8

1.9

V

VDDQ

IO Supply Voltage

 

 

 

1.4

1.5

VDD

V

VOH

Output HIGH Voltage

Note 18

 

VDDQ/2 – 0.12

 

VDDQ/2 + 0.12

V

VOL

Output LOW Voltage

Note 19

 

VDDQ/2 – 0.12

 

VDDQ/2 + 0.12

V

VOH(LOW)

Output HIGH Voltage

IOH = 0.1 mA, Nominal Impedance

 

VDDQ – 0.2

 

VDDQ

V

VOL(LOW)

Output LOW Voltage

IOL = 0.1 mA, Nominal Impedance

 

VSS

 

0.2

V

VIH

Input HIGH Voltage

 

 

 

VREF + 0.1

 

VDDQ + 0.3

V

VIL

Input LOW Voltage

 

 

 

–0.3

 

VREF – 0.1

V

IX

Input Leakage Current

GND VI VDDQ

 

5

 

5

μA

IOZ

Output Leakage Current

GND VI VDDQ, Output Disabled

 

5

 

5

μA

VREF

Input Reference Voltage [20]

Typical Value = 0.75V

 

0.68

0.75

0.95

V

IDD

VDD Operating Supply

VDD = Max,

 

(x8)

 

 

1090

mA

 

 

IOUT = 0 mA,

 

 

 

 

 

 

 

 

 

(x9)

 

 

1090

 

 

 

f = fMAX = 1/tCYC

 

 

 

 

 

 

 

 

 

(x18)

 

 

1115

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(x36)

 

 

1140

 

 

 

 

 

 

 

 

 

 

ISB1

Automatic Power down

Max VDD,

 

(x8)

 

 

405

mA

 

Current

Both Ports Deselected,

 

 

 

 

 

 

 

 

(x9)

 

 

405

 

 

 

VIN VIH or VIN VIL

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(x18)

 

 

405

 

 

 

f = fMAX = 1/tCYC, Inputs Static

 

 

 

 

 

 

 

 

(x36)

 

 

405

 

 

 

 

 

 

 

 

 

 

AC Electrical Characteristics

Over the Operating Range [13]

Parameter

Description

Test Conditions

Min

Typ

Max

Unit

VIH

Input HIGH Voltage

 

VREF + 0.2

V

VIL

Input LOW Voltage

 

VREF – 0.2

V

Notes

17.Power up: Assumes a linear ramp from 0V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD.

18.Output are impedance controlled. IOH = (VDDQ/2)/(RQ/5) for values of 175 ohms <= RQ <= 350 ohms.

19.Output are impedance controlled. IOL = (VDDQ/2)/(RQ/5) for values of 175 ohms <= RQ <= 350 ohms.

20.VREF (min) = 0.68V or 0.46VDDQ, whichever is larger, VREF (max) = 0.95V or 0.54VDDQ, whichever is smaller.

Document Number: 001-12560 Rev. *C

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Contents Configurations FeaturesCY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 Functional DescriptionLogic Block Diagram CY7C1511JV18 Logic Block Diagram CY7C1526JV18CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 Logic Block Diagram CY7C1515JV18 Logic Block Diagram CY7C1513JV18165-Ball FBGA 15 x 17 x 1.4 mm Pinout Pin ConfigurationPin Configuration CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18Pin Definitions Pin Definitions continued CY7C1513JV18, CY7C1515JV18Read Operations Functional OverviewWrite Operations Byte Write OperationsDepth Expansion Concurrent TransactionsProgrammable Impedance Echo ClocksApplication Example CY7C1511JV18, CY7C1526JV18Truth Table ASICWrite Cycle Descriptions Write Cycle Descriptions Test Access Port-Test Clock Disabling the JTAG FeaturePerforming a TAP Reset IEEE 1149.1 Serial Boundary Scan JTAGSAMPLE Z IDCODESAMPLE/PRELOAD BYPASSPage 15 of TAP Controller State DiagramTAP Electrical Characteristics TAP Controller Block DiagramTAP Timing and Test Conditions TAP AC Switching CharacteristicsScan Register Sizes Identification Register DefinitionsInstruction Codes CY7C1511JV18Boundary Scan Order Power Up Waveforms Power Up Sequence in QDR-II SRAMPower Up Sequence DLL ConstraintsDC Electrical Characteristics Electrical CharacteristicsAC Electrical Characteristics Maximum RatingsThermal Resistance CapacitanceAC Test Loads and Waveforms PackageParameter Switching CharacteristicsREAD Switching WaveformsWRITE K K RPS WPSOrdering Information Figure 4. 165-ball FBGA 15 x 17 x 1.40 mm Package DiagramISSUE Document History PageBurst Architecture Document Number ECN NO