Cypress CY7C1515JV18 manual Concurrent Transactions, Depth Expansion, Programmable Impedance

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Concurrent Transactions

CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18

Concurrent Transactions

The read and write ports on the CY7C1513JV18 operates completely independently of one another. As each port latches the address inputs on different clock edges, the user can read or write to any location, regardless of the transaction on the other port. If the ports access the same location when a read follows a write in successive clock cycles, the SRAM delivers the most recent information associated with the specified address location. This includes forwarding data from a write cycle that was initiated on the previous K clock rise.

Read access and write access must be scheduled such that one transaction is initiated on any clock cycle. If both ports are selected on the same K clock rise, the arbitration depends on the previous state of the SRAM. If both ports are deselected, the read port takes priority. If a read was initiated on the previous cycle, the write port takes priority (as read operations can not be initiated on consecutive cycles). If a write was initiated on the previous cycle, the read port takes priority (as write operations can not be initiated on consecutive cycles). Therefore, asserting both port selects active from a deselected state results in alter- nating read or write operations being initiated, with the first access being a read.

Depth Expansion

The CY7C1513JV18 has a port select input for each port. This enables for easy depth expansion. Both port selects are sampled on the rising edge of the positive input clock only (K). Each port select input can deselect the specified port. Deselecting a port does not affect the other port. All pending transactions (read and write) are completed before the device is deselected.

Programmable Impedance

An external resistor, RQ, must be connected between the ZQ pin on the SRAM and VSS to allow the SRAM to adjust its output driver impedance. The value of RQ must be 5X the value of the intended line impedance driven by the SRAM, the allowable range of RQ to guarantee impedance matching with a tolerance of ±15% is between 175Ω and 350Ω, with VDDQ = 1.5V. The output impedance is adjusted every 1024 cycles upon power up to account for drifts in supply voltage and temperature.

Echo Clocks

Echo clocks are provided on the QDR-II to simplify data capture on high-speed systems. Two echo clocks are generated by the QDR-II. CQ is referenced with respect to C and CQ is referenced with respect to C. These are free-running clocks and are synchronized to the output clock of the QDR-II. In the single clock mode, CQ is generated with respect to K and CQ is generated with respect to K. The timing for the echo clocks is shown in the Switching Characteristics on page 23.

DLL

These chips utilize a DLL that is designed to function between 120 MHz and the specified maximum clock frequency. During power up, when the DOFF is tied HIGH, the DLL is locked after 1024 cycles of stable clock. The DLL can also be reset by slowing or stopping the input clocks K and K for a minimum of 30 ns. However, it is not necessary to reset the DLL to lock to the desired frequency. The DLL automatically locks 1024 clock cycles after a stable clock is presented. The DLL may be disabled by applying ground to the DOFF pin. When the DLL is turned off, the device behaves in QDR-I mode (with one cycle latency and a longer access time). For information refer to the application note DLL Considerations in QDRII/DDRII.

Document Number: 001-12560 Rev. *C

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Contents Configurations FeaturesCY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 Functional DescriptionLogic Block Diagram CY7C1511JV18 Logic Block Diagram CY7C1526JV18CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 Logic Block Diagram CY7C1515JV18 Logic Block Diagram CY7C1513JV18165-Ball FBGA 15 x 17 x 1.4 mm Pinout Pin ConfigurationPin Configuration CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18Pin Definitions Pin Definitions continued CY7C1513JV18, CY7C1515JV18Read Operations Functional OverviewWrite Operations Byte Write OperationsDepth Expansion Concurrent TransactionsProgrammable Impedance Echo ClocksApplication Example CY7C1511JV18, CY7C1526JV18Truth Table ASICWrite Cycle Descriptions Write Cycle Descriptions Test Access Port-Test Clock Disabling the JTAG FeaturePerforming a TAP Reset IEEE 1149.1 Serial Boundary Scan JTAGSAMPLE Z IDCODESAMPLE/PRELOAD BYPASSPage 15 of TAP Controller State DiagramTAP Electrical Characteristics TAP Controller Block DiagramTAP Timing and Test Conditions TAP AC Switching CharacteristicsScan Register Sizes Identification Register DefinitionsInstruction Codes CY7C1511JV18Boundary Scan Order Power Up Waveforms Power Up Sequence in QDR-II SRAMPower Up Sequence DLL ConstraintsDC Electrical Characteristics Electrical CharacteristicsAC Electrical Characteristics Maximum RatingsThermal Resistance CapacitanceAC Test Loads and Waveforms PackageParameter Switching CharacteristicsREAD Switching WaveformsWRITE K K RPS WPSOrdering Information Figure 4. 165-ball FBGA 15 x 17 x 1.40 mm Package DiagramISSUE Document History PageBurst Architecture Document Number ECN NO
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