Cypress CY7C1526JV18, CY7C1511JV18 manual Write Cycle Descriptions, CY7C1513JV18, CY7C1515JV18

Page 11
Write Cycle Descriptions

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1511JV18, CY7C1526JV18

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1513JV18, CY7C1515JV18

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Write Cycle Descriptions

 

 

 

The write cycle description table for CY7C1511JV18 and CY7C1513JV18 follows. [2, 10]

 

 

 

 

BWS

0/

 

BWS

1/

K

 

 

 

 

 

Comments

 

 

 

 

 

K

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

NWS0

 

NWS1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

L

 

L

L–H

 

During the data portion of a write sequence:

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1511JV18 both nibbles (D[7:0]) are written into the device.

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1513JV18 both bytes (D[17:0]) are written into the device.

 

 

 

 

L

 

L

L-H

During the data portion of a write sequence:

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1511JV18 both nibbles (D[7:0]) are written into the device.

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1513JV18 both bytes (D[17:0]) are written into the device.

 

 

 

 

L

 

H

L–H

 

During the data portion of a write sequence:

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1511JV18 only the lower nibble (D[3:0]) is written into the device, D[7:4]

 

remains unaltered.

 

 

 

 

 

 

 

 

 

 

CY7C1513JV18 only the lower byte (D[8:0]) is written into the device, D[17:9]

remains unaltered.

 

L

 

H

L–H

During the data portion of a write sequence:

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1511JV18 only the lower nibble (D[3:0]) is written into the device, D[7:4]

 

remains unaltered.

 

 

 

 

 

 

 

 

 

 

CY7C1513JV18 only the lower byte (D[8:0]) is written into the device, D[17:9]

remains unaltered.

 

H

 

L

L–H

 

During the data portion of a write sequence:

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1511JV18 only the upper nibble (D[7:4]) is written into the device, D[3:0]

remains unaltered.

 

 

 

 

 

 

 

 

 

 

CY7C1513JV18 only the upper byte (D[17:9]) is written into the device, D[8:0]

 

remains unaltered.

 

H

 

L

L–H

During the data portion of a write sequence:

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1511JV18 only the upper nibble (D[7:4]) is written into the device, D[3:0]

remains unaltered.

 

 

 

 

 

 

 

 

 

 

CY7C1513JV18 only the upper byte (D[17:9]) is written into the device, D[8:0]

 

remains unaltered.

 

H

 

H

L–H

 

No data is written into the devices during this portion of a write operation.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

H

 

H

L–H

No data is written into the devices during this portion of a write operation.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Write Cycle Descriptions

The write cycle description table for CY7C1526JV18 follows. [2, 10]

BWS0

K

K

Comments

L

L–H

During the Data portion of a write sequence, the single byte (D[8:0]) is written into the device.

L

L–H

During the Data portion of a write sequence, the single byte (D[8:0]) is written into the device.

H

L–H

No data is written into the device during this portion of a write operation.

 

 

 

 

H

L–H

No data is written into the device during this portion of a write operation.

 

 

 

 

Note

10.Is based on a write cycle that was initiated in accordance with the Write Cycle Descriptions table. NWS0, NWS1, BWS0, BWS1, BWS2, and BWS3 can be altered on different portions of a write cycle, as long as the setup and hold requirements are achieved.

Document Number: 001-12560 Rev. *C

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Contents Functional Description FeaturesConfigurations CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 Logic Block Diagram CY7C1511JV18Logic Block Diagram CY7C1526JV18 Logic Block Diagram CY7C1515JV18 Logic Block Diagram CY7C1513JV18165-Ball FBGA 15 x 17 x 1.4 mm Pinout Pin Configuration165-Ball FBGA 15 x 17 x 1.4 mm Pinout Pin Definitions CY7C1511JV18, CY7C1526JV18CY7C1513JV18, CY7C1515JV18 Pin Definitions continued CY7C1513JV18, CY7C1515JV18Byte Write Operations Functional OverviewRead Operations Write OperationsEcho Clocks Concurrent TransactionsDepth Expansion Programmable ImpedanceASIC CY7C1511JV18, CY7C1526JV18Application Example Truth TableWrite Cycle Descriptions Write Cycle Descriptions IEEE 1149.1 Serial Boundary Scan JTAG Disabling the JTAG FeatureTest Access Port-Test Clock Performing a TAP ResetBYPASS IDCODESAMPLE Z SAMPLE/PRELOADPage 15 of TAP Controller State DiagramTAP Electrical Characteristics TAP Controller Block DiagramTAP Timing and Test Conditions TAP AC Switching CharacteristicsCY7C1511JV18 Identification Register DefinitionsScan Register Sizes Instruction CodesBoundary Scan Order DLL Constraints Power Up Sequence in QDR-II SRAMPower Up Waveforms Power Up SequenceMaximum Ratings Electrical CharacteristicsDC Electrical Characteristics AC Electrical CharacteristicsPackage CapacitanceThermal Resistance AC Test Loads and WaveformsParameter Switching CharacteristicsK K RPS WPS Switching WaveformsREAD WRITEOrdering Information Figure 4. 165-ball FBGA 15 x 17 x 1.40 mm Package DiagramECN NO Document History PageISSUE Burst Architecture Document Number