CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18
Functional Overview
The CY7C1511JV18, CY7C1526JV18, CY7C1513JV18, CY7C1515JV18 are synchronous pipelined Burst SRAMs with a read port and a write port. The read port is dedicated to read operations and the write port is dedicated to write operations. Data flows into the SRAM through the write port and flows out through the read port. These devices multiplex the address inputs to minimize the number of address pins required. By having separate read and write ports, the
This device operates with a read latency of one and half cycles when DOFF pin is tied HIGH. When DOFF pin is set LOW or connected to VSS then device behaves in
Accesses for both ports are initiated on the positive input clock
(K). All synchronous input timing is referenced from the rising edge of the input clocks (K and K) and all output timing is refer- enced to the output clocks (C and C, or K and K when in single clock mode).
All synchronous data inputs (D[x:0]) pass through input registers controlled by the input clocks (K and K). All synchronous data outputs (Q[x:0]) pass through output registers controlled by the rising edge of the output clocks (C and C, or K and K when in single clock mode).
All synchronous control (RPS, WPS, BWS[x:0]) inputs pass through input registers controlled by the rising edge of the input clocks (K and K).
CY7C1513JV18 is described in the following sections. The same basic descriptions apply to CY7C1511JV18, CY7C1526JV18 and CY7C1515JV18.
Read Operations
The CY7C1513JV18 is organized internally as four arrays of 1M x 18. Accesses are completed in a burst of four sequential
initiated on two consecutive K clock rises. The internal logic of the device ignores the second read request. Read accesses can be initiated on every other K clock rise. Doing so pipelines the data flow such that data is transferred out of the device on every rising edge of the output clocks (C and C, or K and K when in single clock mode).
When the read port is deselected, the CY7C1513JV18 first completes the pending read transactions. Synchronous internal circuitry automatically
Write Operations
Write operations are initiated by asserting WPS active at the rising edge of the positive input clock (K). On the following K clock rise the data presented to D[17:0] is latched and stored into the lower
(K). Doing so pipelines the data flow such that 18 bits of data can be transferred into the device on every rising edge of the input clocks (K and K).
When deselected, the write port ignores all inputs after the pending write operations have been completed.
Byte Write Operations
Byte write operations are supported by the CY7C1513JV18. A write operation is initiated as described in the Write Operations section. The bytes that are written are determined by BWS0 and BWS1, which are sampled with each set of
Single Clock Mode
The CY7C1511JV18 can be used with a single clock that controls both the input and output registers. In this mode the device recognizes only a single pair of input clocks (K and K) that control both the input and output registers. This operation is identical to the operation if the device had zero skew between the K/K and C/C clocks. All timing parameters remain the same in this mode. To use this mode of operation, the user must tie C and C HIGH at power on. This function is a strap option and not alterable during device operation.
Document Number: | Page 8 of 27 |
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