Cypress CY7C1511JV18 Identification Register Definitions, Scan Register Sizes, Instruction Codes

Page 18
Identification Register Definitions

CY7C1511JV18, CY7C1526JV18

CY7C1513JV18, CY7C1515JV18

Identification Register Definitions

Instruction Field

 

Value

 

Description

CY7C1511JV18

CY7C1526JV18

CY7C1513JV18

CY7C1515JV18

 

 

Revision Number

001

001

001

001

Version number.

(31:29)

 

 

 

 

 

Cypress Device ID

11010011011000100

11010011011001100

11010011011010100

11010011011100100

Defines the type of

(28:12)

 

 

 

 

SRAM.

Cypress JEDEC ID

00000110100

00000110100

00000110100

00000110100

Allows unique

(11:1)

 

 

 

 

identification of

 

 

 

 

 

SRAM vendor.

ID Register

1

1

1

1

Indicates the

Presence (0)

 

 

 

 

presence of an ID

 

 

 

 

 

register.

Scan Register Sizes

Register Name

Bit Size

Instruction

3

 

 

Bypass

1

 

 

ID

32

 

 

Boundary Scan

109

 

 

Instruction Codes

Instruction

Code

Description

EXTEST

000

Captures the input and output ring contents.

 

 

 

IDCODE

001

Loads the ID register with the vendor ID code and places the register between TDI and TDO.

 

 

This operation does not affect SRAM operation.

SAMPLE Z

010

Captures the input and output contents. Places the boundary scan register between TDI and

 

 

TDO. Forces all SRAM output drivers to a High-Z state.

RESERVED

011

Do Not Use: This instruction is reserved for future use.

 

 

 

SAMPLE/PRELOAD

100

Captures the input and output ring contents. Places the boundary scan register between TDI

 

 

and TDO. Does not affect the SRAM operation.

RESERVED

101

Do Not Use: This instruction is reserved for future use.

 

 

 

RESERVED

110

Do Not Use: This instruction is reserved for future use.

 

 

 

BYPASS

111

Places the bypass register between TDI and TDO. This operation does not affect SRAM

 

 

operation.

Document Number: 001-12560 Rev. *C

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Contents CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 FeaturesConfigurations Functional DescriptionLogic Block Diagram CY7C1511JV18 Logic Block Diagram CY7C1526JV18CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 Logic Block Diagram CY7C1513JV18 Logic Block Diagram CY7C1515JV18Pin Configuration 165-Ball FBGA 15 x 17 x 1.4 mm PinoutPin Configuration CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18Pin Definitions CY7C1513JV18, CY7C1515JV18 Pin Definitions continuedWrite Operations Functional OverviewRead Operations Byte Write OperationsProgrammable Impedance Concurrent TransactionsDepth Expansion Echo ClocksTruth Table CY7C1511JV18, CY7C1526JV18Application Example ASICWrite Cycle Descriptions CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 Performing a TAP Reset Disabling the JTAG FeatureTest Access Port-Test Clock IEEE 1149.1 Serial Boundary Scan JTAGSAMPLE/PRELOAD IDCODESAMPLE Z BYPASSTAP Controller State Diagram Page 15 ofTAP Controller Block Diagram TAP Electrical CharacteristicsTAP AC Switching Characteristics TAP Timing and Test ConditionsInstruction Codes Identification Register DefinitionsScan Register Sizes CY7C1511JV18Boundary Scan Order Power Up Sequence Power Up Sequence in QDR-II SRAMPower Up Waveforms DLL ConstraintsAC Electrical Characteristics Electrical CharacteristicsDC Electrical Characteristics Maximum RatingsAC Test Loads and Waveforms CapacitanceThermal Resistance PackageSwitching Characteristics ParameterWRITE Switching WaveformsREAD K K RPS WPSOrdering Information Package Diagram Figure 4. 165-ball FBGA 15 x 17 x 1.40 mmBurst Architecture Document Number Document History PageISSUE ECN NO