Cypress CY7C1548V18 manual Maximum Ratings, DC Electrical Characteristics, Range Ambient

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CY7C1546V18, CY7C1557V18 CY7C1548V18, CY7C1550V18

Maximum Ratings

Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested.

Storage Temperature ................................. –65°C to +150°C

Ambient Temperature with Power Applied.. –55°C to +125°C

Supply Voltage on VDD Relative to GND

–0.5V to +2.9V

Supply Voltage on VDDQ Relative to GND

–0.5V to +VDD

DC Applied to Outputs in High-Z

–0.5V to VDDQ + 0.3V

DC Input Voltage [15]

–0.5V to V + 0.3V

 

 

DD

Current into Outputs (LOW)

 

 

20 mA

Static Discharge Voltage (MIL-STD-883, M. 3015)...

>2001V

Latch up Current

.....................................................

 

 

>200 mA

Operating Range

 

 

 

 

 

 

 

 

 

 

 

Range

 

Ambient

VDD

[15]

VDDQ

[15]

 

Temperature (TA)

 

 

Commercial

 

0°C to +70°C

1.8 ± 0.1V

1.4V to

 

 

 

 

 

VDD

Industrial

 

–40°C to +85°C

 

 

Electrical Characteristics

Over the Operating Range [13]

DC Electrical Characteristics

Parameter

Description

Test Conditions

 

Min

Typ

Max

Unit

VDD

Power Supply Voltage

 

 

 

1.7

1.8

1.9

V

VDDQ

IO Supply Voltage

 

 

 

1.4

1.5

VDD

V

VOH

Output HIGH Voltage

Note 17

 

 

VDDQ/2 – 0.12

 

VDDQ/2 + 0.12

V

VOL

Output LOW Voltage

Note 18

 

 

VDDQ/2 – 0.12

 

VDDQ/2 + 0.12

V

VOH(LOW)

Output HIGH Voltage

IOH = –0.1 mA, Nominal Impedance

 

VDDQ – 0.2

 

VDDQ

V

VOL(LOW)

Output LOW Voltage

IOL = 0.1 mA, Nominal Impedance

 

VSS

 

0.2

V

VIH

Input HIGH Voltage

 

 

 

VREF + 0.1

 

VDDQ + 0.15

V

VIL

Input LOW Voltage

 

 

 

–0.15

 

VREF – 0.1

V

IX

Input Leakage Current

GND VI VDDQ

 

 

–2

 

2

μA

IOZ

Output Leakage Current

GND VI VDDQ, Output Disabled

 

–2

 

2

μA

VREF

Input Reference Voltage [19]

Typical Value = 0.75V

 

 

0.68

0.75

0.95

V

IDD [20]

VDD Operating Supply

VDD = Max,

375MHz

(x8)

 

 

1300

mA

 

 

IOUT = 0 mA,

 

 

 

 

 

 

 

 

 

(x9)

 

 

1300

 

 

 

f = fMAX = 1/tCYC

 

 

 

 

 

 

 

 

 

(x18)

 

 

1300

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(x36)

 

 

1300

 

 

 

 

 

 

 

 

 

 

 

 

 

333MHz

(x8)

 

 

1200

mA

 

 

 

 

 

 

 

 

 

 

 

 

 

(x9)

 

 

1200

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(x18)

 

 

1200

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(x36)

 

 

1200

 

 

 

 

 

 

 

 

 

 

 

 

 

300MHz

(x8)

 

 

1100

mA

 

 

 

 

 

 

 

 

 

 

 

 

 

(x9)

 

 

1100

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(x18)

 

 

1100

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(x36)

 

 

1100

 

 

 

 

 

 

 

 

 

 

Notes

15.Overshoot: VIH(AC) < VDDQ + 0.3V (pulse width less than tCYC/2). Undershoot: VIL(AC) >0.3V (pulse width less than tCYC/2).

16.Power up: assumes a linear ramp from 0V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD.

17.Outputs are impedance controlled. IOH = –(VDDQ/2)/(RQ/5) for values of 175Ω < RQ < 350Ω.

18.Outputs are impedance controlled. IOL = (VDDQ/2)/(RQ/5) for values of 175Ω < RQ < 350Ω.

19.VREF (min) = 0.68V or 0.46VDDQ, whichever is larger. VREF (max) = 0.95V or 0.54VDDQ, whichever is smaller.

20.The operation current is calculated with 50% read cycle and 50% write cycle.

Document Number: 001-06550 Rev. *E

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Contents Features ConfigurationsFunctional Description Selection GuideLogic Block Diagram CY7C1546V18 Logic Block Diagram CY7C1557V18Logic Block Diagram CY7C1548V18 Logic Block Diagram CY7C1550V18Pin Configuration Ball Fbga 15 x 17 x 1.4 mm PinoutCY7C1546V18 8M x CY7C1557V18 8M xCY7C1548V18 4M x CY7C1550V18 2M xPin Definitions Pin Name Pin DescriptionBWS BWS2, BWS3 Synchronous Read or Write Input. WhenPower Supply Inputs to the Core of the Device Power Supply Inputs for the Outputs of the DeviceTDO for Jtag TCK Pin for JtagFunctional Overview Valid Data Indicator Qvld Application ExampleEcho Clocks SRAM#1 SRAM#2Write Cycle Descriptions OperationBWS0 BWS1 CommentsBWS0 BWS0 BWS1 BWS2 BWS3Ieee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram State diagram for the TAP controller followsTAP Controller Block Diagram TAP Electrical CharacteristicsTDI TCKTAP AC Switching Characteristics TAP Timing and Test ConditionsIdentification Register Definitions Scan Register SizesInstruction Codes Register Name Bit SizeBit Number Bump ID Power Up Sequence in DDR-II+ Sram Power Up WaveformsPower Up Sequence DLL ConstraintsElectrical Characteristics DC Electrical CharacteristicsMaximum Ratings Range AmbientAC Electrical Characteristics CapacitanceThermal Resistance Parameter Description Test Conditions Max UnitAC Test Loads and Waveforms AC Test Loads and WaveformsSwitching Characteristics Cypress Consortium Description 375 MHz 333 MHz 300 MHz UnitParameter Min Max DLL TimingSwitching Waveforms Read/Write/Deselect Sequence 29, 30, 31NOP Read NOP WriteOrdering Information 300 Package Diagram Ball Fbga 15 x 17 x 1.4 mmREV ECN No Issue Orig. Description of Change DateDocument History