Cypress CY7C1548V18 manual Switching Waveforms, Read/Write/Deselect Sequence 29, 30, 31, Nop

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CY7C1546V18, CY7C1557V18

CY7C1548V18, CY7C1550V18

Switching Waveforms

Read/Write/Deselect Sequence [29, 30, 31, 32]

Figure 5. Waveform for 2.0 Cycle Read Latency

NOP

1

K

tKH

	READ	READ	NOP	NOP	NOP	WRITE	WRITE	READ	NOP	NOP
	2	3	4	5	6	7	8	9	10	11	12
tKL	tCYC	tKHKH

K

LD tSC tHC

R/W

A	A0	A1		A2	A3	A4
A
	tSA tHA	tQVLD				tQVLD
QVLD					tHD	tHD
					tHD	tHD
					tSD
DQ		Q00	Q01 Q10	Q11	D21	D30 D31	Q40 Q41
DQ
		tCLZ	tDOH	tCHZ
		tCO		tCQD
	(Read Latency = 2.0 Cycles)
		tCCQO		tCQDOH
		tCQOH
CQ			t CCQO		tCQH	tCQHCQH
		tCQOH	t CCQO		tCQH	tCQHCQH
		tCQOH
CQ
						DON’T CARE	UNDEFINED

Notes

29.Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, that is, A0 + 1.

30.Outputs are disabled (High-Z) one clock cycle after a NOP.

31.The third NOP cycle between read to write transition is not necessary for correct device operation when Read Latency = 2.0 cycles; however at high frequency operation, it is required to avoid bus contention.

32.In this example, if address A4 = A3, then data Q40 = D30 and Q41 = D31. Write data is forwarded immediately as read results. This note applies to the whole diagram.

Document Number: 001-06550 Rev. *E

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Contents Features ConfigurationsFunctional Description Selection GuideLogic Block Diagram CY7C1546V18 Logic Block Diagram CY7C1557V18Logic Block Diagram CY7C1548V18 Logic Block Diagram CY7C1550V18Pin Configuration Ball Fbga 15 x 17 x 1.4 mm PinoutCY7C1546V18 8M x CY7C1557V18 8M xCY7C1548V18 4M x CY7C1550V18 2M xPin Definitions Pin Name Pin DescriptionBWS BWS2, BWS3 Synchronous Read or Write Input. WhenPower Supply Inputs to the Core of the Device Power Supply Inputs for the Outputs of the DeviceTDO for Jtag TCK Pin for JtagFunctional Overview Valid Data Indicator Qvld Application ExampleEcho Clocks SRAM#1 SRAM#2Write Cycle Descriptions OperationBWS0 BWS1 CommentsBWS0 BWS0 BWS1 BWS2 BWS3Ieee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram State diagram for the TAP controller followsTAP Controller Block Diagram TAP Electrical CharacteristicsTDI TCKTAP AC Switching Characteristics TAP Timing and Test ConditionsIdentification Register Definitions Scan Register SizesInstruction Codes Register Name Bit SizeBit Number Bump ID Power Up Sequence in DDR-II+ Sram Power Up WaveformsPower Up Sequence DLL ConstraintsElectrical Characteristics DC Electrical CharacteristicsMaximum Ratings Range AmbientAC Electrical Characteristics CapacitanceThermal Resistance Parameter Description Test Conditions Max UnitAC Test Loads and Waveforms AC Test Loads and WaveformsSwitching Characteristics Cypress Consortium Description 375 MHz 333 MHz 300 MHz UnitParameter Min Max DLL TimingSwitching Waveforms Read/Write/Deselect Sequence 29, 30, 31NOP Read NOP WriteOrdering Information 300 Package Diagram Ball Fbga 15 x 17 x 1.4 mmECN No Issue Orig. Description of Change Date Document HistoryREV